agostini01 / FPGA_Neural-Network

Related projects ⓘ

Alternatives and complementary repositories for FPGA_Neural-Network

• brianhill11 / FPGA-CNN
  This repo is for ECE44x (Fall2015-Spring2016)
  ☆19Updated 6 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆32Updated 6 years ago
• StefanSredojevic / Deep-Neural-Network-Hardware-Accelerator
  SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…
  ☆98Updated 4 years ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆40Updated 4 years ago
• ziyan / altera-de2-ann
  Artificial Neural Network on Altera DE2
  ☆32Updated 9 years ago
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆73Updated 5 years ago
• xiangze / CNN_FPGA
  verilog CNN generator for FPGA
  ☆32Updated 3 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆54Updated 4 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆44Updated 8 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆85Updated 3 years ago
• hukenovs / fp23fftk
  Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
  ☆55Updated 2 years ago
• silicontalks01 / OpenDLA
  A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.
  ☆15Updated 7 years ago
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆44Updated 10 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆63Updated this week
• shaneleonard / neural-hardware
  Verilog library for implementing neural networks.
  ☆24Updated 10 years ago
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆58Updated 7 years ago
• diaoenmao / FPGA-CNN
  FPGA implementation of Cellular Neural Network (CNN)
  ☆136Updated 6 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆92Updated 5 years ago
• Xilinx / RFNoC-HLS-NeuralNet
  ☆104Updated 5 years ago
• PeterOgden / overlay_tutorial
  Premade bitstreams and block designs to complemented the PYNQ overlay tutorial
  ☆39Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 6 months ago
• freecores / robust_axi_fabric
  Generic AXI interconnect fabric
  ☆13Updated 10 years ago
• hillhao / PYNQ-project
  PYNQ, Neural network Language model, Overlay
  ☆102Updated 5 years ago
• sfox14 / pynq-ekf
  A multi-board Extended Kalman Filter (EKF)
  ☆28Updated 6 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• cebarnes / cordic
  An implementation of the CORDIC algorithm in Verilog.
  ☆83Updated 6 years ago
• oprecomp / DDR4_controller
  ☆47Updated 3 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆28Updated last month
• alan4186 / Hardware-CNN
  A convolutional neural network implemented in hardware (verilog)
  ☆151Updated 7 years ago