agostini01 / FPGA_Neural-NetworkLinks
The objective is to implement a Neural Network in VHDL code. It is aiming the Cyclone II FPGA Starter Development Kit hardware, but the Neural Network part is meant to be generic, thus it can be used along with different hardware setups.
☆29Updated 8 years ago
Alternatives and similar repositories for FPGA_Neural-Network
Users that are interested in FPGA_Neural-Network are comparing it to the libraries listed below
Sorting:
- This repo is for ECE44x (Fall2015-Spring2016)☆20Updated 7 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆34Updated 7 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆49Updated 9 years ago
- implementing a Recurrent Neural Network with binarized weight format on FPGA☆22Updated 7 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 5 years ago
- Verilog Content Addressable Memory Module☆107Updated 3 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).☆60Updated 2 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆110Updated 5 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆64Updated 8 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 4 months ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- round robin arbiter☆74Updated 10 years ago
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs☆48Updated 7 years ago
- A convolutional neural network implemented in hardware (verilog)☆159Updated 7 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆64Updated 8 years ago
- ☆35Updated 7 years ago
- ☆107Updated 5 years ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated 10 months ago
- Generic FIFO implementation with optional FWFT☆58Updated 5 years ago
- Simple hash table on Verilog (SystemVerilog)☆49Updated 9 years ago
- ☆19Updated last year
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆49Updated 7 years ago
- EE 287 2012 Fall☆30Updated 12 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago