The objective is to implement a Neural Network in VHDL code. It is aiming the Cyclone II FPGA Starter Development Kit hardware, but the Neural Network part is meant to be generic, thus it can be used along with different hardware setups.
☆29Feb 4, 2017Updated 9 years ago
Alternatives and similar repositories for FPGA_Neural-Network
Users that are interested in FPGA_Neural-Network are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Voice Recognition using FPGA-Based Neural Networks☆15Jul 6, 2016Updated 9 years ago
- VHDL for basic floating-point operations.☆31Oct 2, 2018Updated 7 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago
- An RS232 communication controller implemented in VHDL☆16Aug 17, 2014Updated 11 years ago
- ☆22Dec 26, 2016Updated 9 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs☆49Aug 31, 2017Updated 8 years ago
- A basic SD Card SPI interface in VHDL, supports SD V1, V2 and SDHC☆26Sep 29, 2014Updated 11 years ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- Photoshop Actions to mimic Instagram filters☆11Jan 3, 2017Updated 9 years ago
- high level VHDL floating point library for synthesis in fpga☆18Dec 18, 2025Updated 4 months ago
- A VHDL implementation of an Ethernet MAC☆17Aug 13, 2012Updated 13 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆24Apr 27, 2026Updated last week
- Projects in C/C++ for STM32F103C8T6, STM32F030F4P6 and STM32F746ZGT6 32-bit ARM Microcontrollers☆11Feb 3, 2026Updated 3 months ago
- UartOscilloscope(Uart介面示波器)☆11Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Command line tool for Tsinghua University network authentication☆27Aug 23, 2019Updated 6 years ago
- Network packet parser generator☆53Sep 11, 2020Updated 5 years ago
- NN on FPGA☆22Jun 10, 2017Updated 8 years ago
- A pipelined cordic algoithm for computing cos(angle) and sin(angle) in verilog☆19May 29, 2017Updated 8 years ago
- ☆11Apr 6, 2016Updated 10 years ago
- A pure C Bitset implementation.☆20Jun 25, 2016Updated 9 years ago
- ☆12Jul 16, 2023Updated 2 years ago
- implementing a Recurrent Neural Network with binarized weight format on FPGA☆22Sep 3, 2017Updated 8 years ago
- GPS receiver for gnuradio☆13Mar 11, 2017Updated 9 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- GIAnT, the Generic Implementation ANalysis Toolkit☆12Jul 4, 2018Updated 7 years ago
- Time to Digital Converter (TDC)☆36Dec 27, 2020Updated 5 years ago
- Neural Network for Pattern Recognition on an FPGA. Project for Education. Video lectures explain training of the network and FPGA impleme…☆23May 15, 2024Updated last year
- Plotting widget for imgui☆10Oct 9, 2020Updated 5 years ago
- Haskell to D3.js binding by deep EDSL approach.☆23Sep 20, 2014Updated 11 years ago
- A Modular System for Flexible, High-Performance Traffic http://www.ict-mplane.eu/☆24Oct 4, 2018Updated 7 years ago
- A collection of MyHDL cores and tools for complex digital circuit design☆87Dec 23, 2018Updated 7 years ago
- Data Flow Matrix Machines. Generalization of recurrent neural networks.☆15Dec 24, 2024Updated last year
- unsigned Radix-2 SRT division,基2除法☆16May 12, 2015Updated 10 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- MPU6050 interface for fpga☆11May 9, 2020Updated 5 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆11Feb 11, 2021Updated 5 years ago
- ☆12Sep 5, 2017Updated 8 years ago
- Reference implementations of the GIMLI permutation☆15Jul 9, 2017Updated 8 years ago
- Hardware CD/CI and Development Containers 🚢☆11Jul 20, 2022Updated 3 years ago
- VHDL Library for implementing common DSP functionality.☆31Oct 5, 2018Updated 7 years ago
- ☆15Jun 7, 2022Updated 3 years ago