CommonEvaluationPlatform / CEPLinks
The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.
☆26Updated last year
Alternatives and similar repositories for CEP
Users that are interested in CEP are comparing it to the libraries listed below
Sorting:
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆96Updated last year
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆143Updated last week
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated 3 weeks ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated last month
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆67Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated last year
- RISC-V Nox core☆71Updated 5 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- sram/rram/mram.. compiler☆43Updated 2 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last month
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 2 weeks ago
- RISC-V Verification Interface☆134Updated 2 weeks ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆43Updated last year
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆28Updated 4 years ago
- Python library for operations with VCD and other digital wave files☆53Updated last month
- ☆58Updated 8 months ago
- Open source process design kit for 28nm open process☆69Updated last year
- Open source RTL simulation acceleration on commodity hardware☆33Updated 2 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆53Updated 4 months ago
- BlackParrot on Zynq☆47Updated last week
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆120Updated 4 years ago
- ☆110Updated last month
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆135Updated last month
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 5 months ago