VLSIDA / OpenCacheLinks
An open-source custom cache generator.
☆34Updated last year
Alternatives and similar repositories for OpenCache
Users that are interested in OpenCache are comparing it to the libraries listed below
Sorting:
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago
- For contributions of Chisel IP to the chisel community.☆67Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- The multi-core cluster of a PULP system.☆109Updated 2 weeks ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- Mutation Cover with Yosys (MCY)☆88Updated this week
- Simple runtime for Pulp platforms☆49Updated last week
- ☆33Updated 2 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- HW Design Collateral for Caliptra RoT IP☆115Updated this week
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- A SystemVerilog source file pickler.☆60Updated last year
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month
- ☆114Updated 3 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆76Updated last year
- Demo SoC for SiliconCompiler.☆62Updated 2 weeks ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- 64-bit multicore Linux-capable RISC-V processor☆99Updated 6 months ago
- Hardware generator debugger☆77Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated this week
- ☆56Updated 3 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆126Updated last year
- Generic Register Interface (contains various adapters)☆133Updated last month
- FPGA tool performance profiling☆103Updated last year