Alternatives and similar repositories for HybridDBT:

Users that are interested in HybridDBT are comparing it to the libraries listed below

• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆31Updated 9 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆35Updated 3 years ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆78Updated last week
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 3 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆82Updated 10 months ago
• embecosm / embecosm-toolchain-releases
  ☆16Updated 6 months ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 5 years ago
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆41Updated 7 years ago
• vortexgpgpu / skybox
  Vortex Graphics
  ☆71Updated 4 months ago
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆34Updated 3 years ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆32Updated 2 weeks ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆51Updated this week
• chipsalliance / tilelink
  ☆27Updated 2 months ago
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆26Updated last week
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆57Updated 3 months ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 7 years ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆44Updated last year
• riscv / riscv-CMOs
  ☆84Updated 2 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆79Updated 4 months ago
• vherdt / riscv-vp
  RISC-V Virtual Prototype
  ☆40Updated 3 years ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 8 months ago
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆45Updated 9 months ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆84Updated this week
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆90Updated this week
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆139Updated 2 weeks ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆72Updated 5 years ago