bojackchen / digital-flow
This is a tutorial on standard digital design flow
☆75Updated 3 years ago
Alternatives and similar repositories for digital-flow:
Users that are interested in digital-flow are comparing it to the libraries listed below
- Introductory course into static timing analysis (STA).☆90Updated 5 months ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆170Updated 5 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- ☆151Updated last month
- EE 260 Winter 2017: Advanced VLSI Design☆62Updated 8 years ago
- A verilog implementation for Network-on-Chip☆72Updated 7 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆61Updated 5 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆30Updated 4 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆41Updated 9 months ago
- ☆41Updated 7 months ago
- SystemVerilog modules and classes commonly used for verification☆47Updated 3 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆53Updated last month
- Logic synthesis and ABC based optimization☆49Updated this week
- Project repo for the POSH on-chip network generator☆45Updated 3 weeks ago
- ☆31Updated 5 years ago
- General Purpose AXI Direct Memory Access☆48Updated 11 months ago
- ideas and eda software for vlsi design☆49Updated last week
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆247Updated last month
- Implementing Different Adder Structures in Verilog☆64Updated 5 years ago
- ☆48Updated 2 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆80Updated last year
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆95Updated last year
- Python Tool for UVM Testbench Generation☆52Updated 10 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆98Updated 4 years ago
- ☆22Updated 2 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆71Updated last week
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago