bojackchen / digital-flowLinks
This is a tutorial on standard digital design flow
☆80Updated 4 years ago
Alternatives and similar repositories for digital-flow
Users that are interested in digital-flow are comparing it to the libraries listed below
Sorting:
- Introductory course into static timing analysis (STA).☆99Updated 5 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated last week
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆195Updated 5 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆67Updated 9 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆73Updated 5 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆183Updated last year
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- A verilog implementation for Network-on-Chip☆78Updated 7 years ago
- SystemVerilog modules and classes commonly used for verification☆53Updated last month
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆38Updated 5 years ago
- ☆46Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆53Updated 4 years ago
- ideas and eda software for vlsi design☆51Updated 2 weeks ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆75Updated 4 years ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆43Updated last year
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆140Updated 7 years ago
- Network on Chip Implementation written in SytemVerilog☆196Updated 3 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆275Updated 2 weeks ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated last year
- A complete open-source design-for-testing (DFT) Solution☆173Updated 3 months ago
- SRAM☆22Updated 5 years ago
- ☆218Updated 9 months ago
- ☆183Updated 4 years ago
- Project repo for the POSH on-chip network generator☆52Updated 9 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆75Updated last month
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆71Updated last year
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆28Updated 4 years ago