JakodYuan / SVK-AMBA-VIP

Related projects ⓘ

Alternatives and complementary repositories for SVK-AMBA-VIP

• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆27Updated last year
• wanderingnail / AXI_DMA
  ☆16Updated 2 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆21Updated 3 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆10Updated 4 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆15Updated 10 years ago
• Lampro-Mellon / apb-uart-uvm-env
  ☆34Updated last year
• Gateway91 / AHB-APB_Bridge_UVM_Env
  AHB-APB UVM Verification Environment
  ☆17Updated 9 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆26Updated 4 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆17Updated 5 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆28Updated 4 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆20Updated 2 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆17Updated 4 months ago
• nahidrn / axi_vip_master
  Sample UVM code for axi ram dut
  ☆28Updated 2 years ago
• deekshithkrishnegowda / AHB2APB-bridge-IP-core-verification
  Maven Silicon Project
  ☆18Updated 6 years ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆30Updated 4 years ago
• hengfengzhang / soc
  soc integration script and integration smoke script
  ☆21Updated 2 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆56Updated 3 years ago
• muneebullashariff / apb_vip
  Verification IP for APB protocol
  ☆25Updated 4 years ago
• dpc525 / uvm_tb_gen
  generate UVM testbench using python
  ☆26Updated 6 years ago
• wbbbbbb123 / Sram-controller-design-based-on-AHB-bus
  ☆18Updated 2 years ago
• muneebullashariff / spi_vip
  Verification IP for SPI protocol
  ☆16Updated 4 years ago
• marshall-999 / UVMReference
  This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).
  ☆10Updated 3 years ago
• wbbbbbb123 / UVM-based-AHB-bus-SRAM-controller-design-verification-platform-design
  ☆14Updated 2 years ago
• xdesigns / 4way-cache
  Verilog cache implementation of 4-way FIFO 16k Cache
  ☆19Updated 11 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆37Updated 4 years ago
• Jon3Y / AMBA
  AHB/APB SRAM Inf, VCS&Verdi Sim.
  ☆12Updated 2 years ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆13Updated 6 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆31Updated 2 years ago
• Mohamed-Younis / SPI-UVM-Testbench
  ☆16Updated 3 years ago