Simple AMBA VIP, Include axi/ahb/apb
☆36Jul 4, 2024Updated 2 years ago
Alternatives and similar repositories for SVK-AMBA-VIP
Users that are interested in SVK-AMBA-VIP are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- AXI Verification using UVM Testbench☆16Oct 20, 2024Updated last year
- ☆27Oct 1, 2026Updated last week
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆26Mar 25, 2025Updated last year
- SystemVerilog、Verilog、UVM☆17Jun 23, 2020Updated 6 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 5 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆52Nov 3, 2023Updated 2 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 3 years ago
- Awesome ASIC design verification☆368Feb 9, 2022Updated 4 years ago
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆29Jan 6, 2026Updated 9 months ago
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆22Apr 12, 2026Updated 6 months ago
- Development of AXI4 Accelerated VIP☆33Apr 3, 2023Updated 3 years ago
- ☆22Sep 26, 2025Updated last year
- amba3 apb/axi vip☆53Feb 24, 2015Updated 11 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆40Nov 24, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆32Jun 1, 2022Updated 4 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆42Sep 21, 2021Updated 5 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 6 years ago
- This is the repository for the IEEE version of the book☆87Sep 29, 2020Updated 6 years ago
- SoC Based on ARM Cortex-M3☆40May 16, 2025Updated last year
- This is for uvm_tb_gen☆60Feb 13, 2025Updated last year
- A simple spidergon network-on-chip with wormhole switching feature☆13Mar 22, 2021Updated 5 years ago
- APB VIP (UVM)☆18Sep 6, 2018Updated 8 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆203Jul 23, 2018Updated 8 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆25Apr 25, 2025Updated last year
- General Purpose IO with APB4 interface☆17May 10, 2024Updated 2 years ago
- Direct Access Memory for MPSoC☆13Aug 7, 2026Updated 2 months ago
- SystemVerilog VIP for AMBA APB protocol☆91Nov 11, 2021Updated 4 years ago
- ☆25Feb 10, 2024Updated 2 years ago
- Novel GUI Based UVM Testbench Template Builder☆156Apr 14, 2021Updated 5 years ago
- AMBA AXI VIP☆478Oct 1, 2026Updated last week
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Aug 9, 2026Updated 2 months ago
- Support code for DVCon 2021 paper submission☆13Mar 1, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It …☆32Nov 21, 2020Updated 5 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- The official NaplesPU hardware code repository☆37Jul 27, 2019Updated 7 years ago
- my UVM training projects☆40Mar 14, 2019Updated 7 years ago
- Hardware Formal Verification☆18Aug 10, 2020Updated 6 years ago
- vector accelerating unit☆37Dec 1, 2020Updated 5 years ago
- ☆13Mar 10, 2023Updated 3 years ago