Cortex M0 based SoC
☆76Sep 9, 2021Updated 4 years ago
Alternatives and similar repositories for CortexM0_SoC
Users that are interested in CortexM0_SoC are comparing it to the libraries listed below
Sorting:
- Step by step tutorial for building CortexM0 SoC☆39Mar 29, 2022Updated 3 years ago
- ☆21Apr 28, 2021Updated 4 years ago
- ☆11May 31, 2016Updated 9 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Dec 8, 2012Updated 13 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- ☆38Aug 12, 2015Updated 10 years ago
- UVM VIP architecture generator☆20Aug 24, 2020Updated 5 years ago
- Cortex_m0软核源码,可以在FPGA上直接跑,包含UART、定时器这些外设,可以用keil写用户代码。可以看看《Cortex-M0 全可编程SoC原理及实现》这本书☆26Mar 15, 2021Updated 4 years ago
- Altera Cyclone IV FPGA project for the PCIe LimeSDR board☆42Nov 3, 2022Updated 3 years ago
- Jude's vimrc for DV work(fine tuning for SV/UVM)☆21Mar 12, 2024Updated last year
- Generic AXI to AHB bridge☆18Jul 17, 2014Updated 11 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- ☆10Aug 15, 2019Updated 6 years ago
- Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.☆16May 28, 2021Updated 4 years ago
- GPS&BD2卫星导航系统模拟信号源☆11Aug 6, 2015Updated 10 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- ☆12Nov 11, 2015Updated 10 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆22Jan 31, 2020Updated 6 years ago
- ☆74Jan 19, 2016Updated 10 years ago
- Verification of Ethernet Switch System Verilog☆11Oct 21, 2016Updated 9 years ago
- NeoPixel LED Controller | NeoPixel LED 控制器 | 基於MAX10 FPGA的音樂全彩光立方LED控制器☆12Jan 4, 2022Updated 4 years ago
- ☆14Feb 24, 2025Updated last year
- AMBA bus lecture material☆512Jan 21, 2020Updated 6 years ago
- Mirror of the Universal Verification Methodology from sourceforge☆37Jan 21, 2015Updated 11 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- RiscSoC 是一个芯片集成项目,包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成,部分 SoC 使用的自己设计的内核☆12Apr 26, 2022Updated 3 years ago
- ☆20Aug 22, 2022Updated 3 years ago
- 基于arm cortex-m0内核的xillinx fpga sopc工程项目☆13May 28, 2019Updated 6 years ago
- SoC Based on ARM Cortex-M3☆37May 16, 2025Updated 9 months ago
- PN432 driver for STM32 using CMSIS☆14Jun 30, 2016Updated 9 years ago
- Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus☆16Oct 21, 2020Updated 5 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- kintex7 ov13850 fpga mipi camera☆20Dec 2, 2025Updated 3 months ago
- ☆19Aug 11, 2022Updated 3 years ago
- ☆41Apr 4, 2021Updated 4 years ago
- Just A Really Very Impressive Systemverilog UVM Kit☆18Dec 17, 2020Updated 5 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆20Jul 29, 2014Updated 11 years ago
- OV7670 (Verilog HDL)Drive for FPGA☆18Mar 4, 2019Updated 7 years ago