Alternatives and similar repositories for SoC-DV

Users that are interested in SoC-DV are comparing it to the libraries listed below

• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆30Updated last week
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆44Updated 5 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆27Updated 5 years ago
• yvnr4you / SDRAM-Verification
  This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …
  ☆25Updated 8 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆32Updated 4 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆34Updated 8 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆32Updated 2 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆25Updated 3 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆66Updated 4 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆64Updated 4 years ago
• dpc525 / uvm_tb_gen
  generate UVM testbench using python
  ☆27Updated 7 years ago
• avashist003 / FIFO_SystemVerilog_Assertion
  Synchronous FIFO design & verification using systemVerilog Assertions
  ☆16Updated 3 years ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆55Updated last year
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆24Updated 5 years ago
• amamory-verification / uvm-basics
  my UVM training projects
  ☆33Updated 6 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆54Updated 8 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 4 years ago
• designsolver / ahb3_uvm_tb
  AMBA 3 AHB UVM TB
  ☆32Updated 6 years ago
• Mohamed-Younis / SPI-UVM-Testbench
  ☆22Updated 4 years ago
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆39Updated 4 years ago
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆74Updated 3 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆60Updated 4 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆25Updated last year
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆22Updated 4 months ago
• techvinodreddy / UART-IP-CORE16550A-Verification-UVM
  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …
  ☆17Updated 3 years ago
• akzare / Async_FIFO_Verification
  Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
  ☆50Updated 4 years ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆34Updated 5 years ago
• seabeam / yuu_vip_gen
  UVM VIP architecture generator
  ☆19Updated 4 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆50Updated last year
• yuravg / uvm_tb_cross_bar
  SystemVerilog UVM testbench example
  ☆31Updated last year