feifan1996 / RiscSoCLinks
RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核
☆10Updated 3 years ago
Alternatives and similar repositories for RiscSoC
Users that are interested in RiscSoC are comparing it to the libraries listed below
Sorting:
- ☆19Updated 2 years ago
- ☆14Updated 2 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆13Updated 3 years ago
- AXI Interconnect☆49Updated 3 years ago
- Generic AXI to AHB bridge☆17Updated 10 years ago
- ☆36Updated 9 years ago
- SPI interface connect to APB BUS with Verilog HDL☆32Updated 3 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- Verification IP for APB protocol☆66Updated 4 years ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- AXI总线连接器☆97Updated 5 years ago
- ☆20Updated 2 years ago
- An uvm verification env for ahb2apb bridge☆53Updated 4 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆21Updated 3 years ago
- ☆10Updated 4 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆14Updated 2 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆23Updated 2 years ago
- PCIE 5.0 Graduation project (Verification Team)☆72Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆60Updated 2 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆32Updated 2 years ago
- AHB to APB Bridge VIP☆29Updated 6 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- ☆40Updated last year
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆18Updated last year
- ☆64Updated 9 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- APB to I2C☆41Updated 10 years ago