chengquan / IC_FLOWLinks
☆16Updated last year
Alternatives and similar repositories for IC_FLOW
Users that are interested in IC_FLOW are comparing it to the libraries listed below
Sorting:
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 4 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆23Updated 2 years ago
- ☆39Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- ☆34Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆19Updated last year
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆37Updated last year
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- ☆15Updated last year
- Verilog and matlab implementation of tanh using Cordic algorithm☆10Updated 5 years ago
- AXI总线连接器☆99Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆118Updated last month
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆12Updated 2 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- An LeNet RTL implement onto FPGA☆48Updated 7 years ago
- syn script for DC Compiler☆13Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆162Updated 5 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .☆12Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆47Updated 7 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- IC Verification & SV Demo☆54Updated 3 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆60Updated last year
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year