chengquan / IC_FLOWLinks
☆19Updated last month
Alternatives and similar repositories for IC_FLOW
Users that are interested in IC_FLOW are comparing it to the libraries listed below
Sorting:
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆25Updated 7 years ago
- ☆43Updated 4 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆22Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆176Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆68Updated last year
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆41Updated 2 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆38Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆141Updated 6 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- ☆121Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆234Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆107Updated 5 years ago
- 3×3脉动阵列乘法器☆48Updated 6 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆46Updated 3 years ago
- Convolutional Neural Network RTL-level Design☆72Updated 4 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- AXI总线连接器☆105Updated 5 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆33Updated last year
- ☆37Updated 6 years ago
- IC Verification & SV Demo☆54Updated 4 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆16Updated 4 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆28Updated last year
- An LeNet RTL implement onto FPGA☆50Updated 7 years ago
- syn script for DC Compiler☆14Updated 3 years ago
- ☆14Updated 2 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆66Updated 7 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆120Updated 4 months ago