HonkW93 / automatic-verilogLinks
automatic-verilog based on vimscript
☆279Updated 2 years ago
Alternatives and similar repositories for automatic-verilog
Users that are interested in automatic-verilog are comparing it to the libraries listed below
Sorting:
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆234Updated 2 years ago
- this repository is vim cfg for verilog.☆54Updated last year
- AMBA bus lecture material☆490Updated 5 years ago
- Awesome ASIC design verification☆337Updated 3 years ago
- AMBA AXI VIP☆434Updated last year
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆189Updated 7 years ago
- uvm AXI BFM(bus functional model)☆264Updated 12 years ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆589Updated 4 years ago
- Reference examples and short projects using UVM Methodology☆286Updated 3 years ago
- This is the main repository for all the examples for the book Practical UVM☆212Updated 5 years ago
- Novel GUI Based UVM Testbench Template Builder☆147Updated 4 years ago
- commit rtl and build cosim env☆36Updated last year
- AXI协议规范中文翻译版☆166Updated 3 years ago
- ☆153Updated 3 weeks ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- Some useful documents of Synopsys☆92Updated 4 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆402Updated 3 months ago
- UVM AHB VIP☆90Updated 3 months ago
- ☆75Updated 4 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆144Updated last year
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆110Updated 2 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆134Updated 4 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆134Updated 8 years ago
- Source code repo for UVM Tutorial for Candy Lovers☆204Updated 8 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆157Updated 5 years ago
- AXI总线连接器☆105Updated 5 years ago
- 数字IC秋招项目、手撕代码☆39Updated last year
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆153Updated 7 years ago
- ☆214Updated 6 months ago
- training labs and examples☆442Updated 3 years ago