automatic-verilog based on vimscript
☆291Oct 24, 2023Updated 2 years ago
Alternatives and similar repositories for automatic-verilog
Users that are interested in automatic-verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆116Oct 31, 2023Updated 2 years ago
- Verilog/SystemVerilog Syntax and Omni-completion☆424Aug 3, 2026Updated last month
- ☆77Jul 30, 2021Updated 5 years ago
- verilog filetype plugin to enable emacs verilog-mode autos☆25Apr 24, 2022Updated 4 years ago
- Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.☆290Aug 31, 2026Updated last week
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 3 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆75Nov 22, 2019Updated 6 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆246Jul 16, 2023Updated 3 years ago
- ☆247Jun 25, 2025Updated last year
- this repository is vim cfg for verilog.☆56Aug 28, 2026Updated last week
- Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3☆37Aug 6, 2013Updated 13 years ago
- Synopsys License patcher☆48Sep 12, 2024Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,682Aug 27, 2026Updated last week
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆208Jan 28, 2026Updated 7 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Must-have verilog systemverilog modules☆2,018Mar 12, 2026Updated 5 months ago
- Novel GUI Based UVM Testbench Template Builder☆156Apr 14, 2021Updated 5 years ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,851Mar 24, 2021Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆209Jun 3, 2026Updated 3 months ago
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 4 years ago
- Verilog AXI components for FPGA implementation☆2,128Feb 27, 2025Updated last year
- verilog filetype plugin to enable emacs verilog-mode autos☆17Apr 24, 2022Updated 4 years ago
- AMBA bus lecture material☆552Jan 21, 2020Updated 6 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆35Jul 9, 2025Updated last year
- The Ultra-Low Power RISC-V Core☆1,908Aug 6, 2025Updated last year
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,929Updated this week
- An Ethernet MAC conforming to IEEE 802.3☆24May 13, 2017Updated 9 years ago
- Common SystemVerilog components☆793Updated this week
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆152Jan 23, 2024Updated 2 years ago
- IC design and development should be faster，simpler and more reliable☆2,015Dec 31, 2021Updated 4 years ago
- SoC Based on ARM Cortex-M3☆40May 16, 2025Updated last year
- ☆37Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Verdi like, verilog code signal trace and show hierarchy script☆19Oct 16, 2019Updated 6 years ago
- RTL, Cmodel, and testbench for NVDLA☆2,147Mar 2, 2022Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆36Mar 9, 2017Updated 9 years ago
- OpenXuantie - OpenC910 Core☆1,472Jun 28, 2024Updated 2 years ago
- OpenTitan: Open source silicon root of trust☆3,630Updated this week
- UVM Generator☆50May 9, 2024Updated 2 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago