HonkW93 / automatic-verilogLinks
automatic-verilog based on vimscript
☆267Updated last year
Alternatives and similar repositories for automatic-verilog
Users that are interested in automatic-verilog are comparing it to the libraries listed below
Sorting:
- this repository is vim cfg for verilog.☆50Updated last year
- AMBA bus lecture material☆454Updated 5 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆211Updated 2 years ago
- Awesome ASIC design verification☆316Updated 3 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆175Updated 7 years ago
- AMBA AXI VIP☆413Updated last year
- uvm AXI BFM(bus functional model)☆251Updated 12 years ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆560Updated 3 years ago
- Novel GUI Based UVM Testbench Template Builder☆140Updated 4 years ago
- Reference examples and short projects using UVM Methodology☆277Updated 3 years ago
- This is the main repository for all the examples for the book Practical UVM☆201Updated 4 years ago
- ☆148Updated 3 weeks ago
- ☆72Updated 4 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆359Updated last year
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆138Updated last year
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆128Updated 4 years ago
- Some useful documents of Synopsys☆77Updated 3 years ago
- This is for uvm_tb_gen☆33Updated 5 months ago
- AXI DMA 32 / 64 bits☆116Updated 11 years ago
- The UVM written in Python☆445Updated 3 weeks ago
- commit rtl and build cosim env☆36Updated last year
- AXI协议规范中文翻译版☆159Updated 3 years ago
- AXI总线连接器☆103Updated 5 years ago
- Source code repo for UVM Tutorial for Candy Lovers☆193Updated 8 years ago
- 数字IC秋招项目、手撕代码☆36Updated last year
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆152Updated 5 years ago
- training labs and examples☆431Updated 3 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆144Updated 7 years ago
- Verilog/SystemVerilog Syntax and Omni-completion☆401Updated 9 months ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆122Updated 7 years ago