automatic-verilog based on vimscript
☆290Oct 24, 2023Updated 2 years ago
Alternatives and similar repositories for automatic-verilog
Users that are interested in automatic-verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆114Oct 31, 2023Updated 2 years ago
- ☆76Jul 30, 2021Updated 4 years ago
- Verilog/SystemVerilog Syntax and Omni-completion☆418Oct 13, 2024Updated last year
- verilog filetype plugin to enable emacs verilog-mode autos☆25Apr 24, 2022Updated 4 years ago
- Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.☆287Apr 14, 2026Updated 2 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 3 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆74Nov 22, 2019Updated 6 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆245Jul 16, 2023Updated 2 years ago
- ☆238Jun 25, 2025Updated last year
- this repository is vim cfg for verilog.☆56Apr 24, 2026Updated 2 months ago
- Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3☆37Aug 6, 2013Updated 12 years ago
- ☆35Jul 9, 2025Updated 11 months ago
- Synopsys License patcher☆42Sep 12, 2024Updated last year
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆203Jan 28, 2026Updated 5 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Must-have verilog systemverilog modules☆1,989Mar 12, 2026Updated 3 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,616Updated this week
- Novel GUI Based UVM Testbench Template Builder☆155Apr 14, 2021Updated 5 years ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,849Mar 24, 2021Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆207Jun 3, 2026Updated last month
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 3 years ago
- The Ultra-Low Power RISC-V Core☆1,867Aug 6, 2025Updated 11 months ago
- Verilog AXI components for FPGA implementation☆2,082Feb 27, 2025Updated last year
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- verilog filetype plugin to enable emacs verilog-mode autos☆17Apr 24, 2022Updated 4 years ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,877Jun 22, 2026Updated 2 weeks ago
- AMBA bus lecture material☆538Jan 21, 2020Updated 6 years ago
- Common SystemVerilog components☆764Updated this week
- An Ethernet MAC conforming to IEEE 802.3☆24May 13, 2017Updated 9 years ago
- IC design and development should be faster,simpler and more reliable☆2,002Dec 31, 2021Updated 4 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆150Jan 23, 2024Updated 2 years ago
- SoC Based on ARM Cortex-M3☆40May 16, 2025Updated last year
- OpenXuantie - OpenC910 Core☆1,448Jun 28, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆35Updated this week
- Verdi like, verilog code signal trace and show hierarchy script☆18Oct 16, 2019Updated 6 years ago
- OpenTitan: Open source silicon root of trust☆3,502Updated this week
- RTL, Cmodel, and testbench for NVDLA☆2,114Mar 2, 2022Updated 4 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- UVM Generator☆50May 9, 2024Updated 2 years ago