drom / spiLinks
spi memory controller
☆22Updated 9 years ago
Alternatives and similar repositories for spi
Users that are interested in spi are comparing it to the libraries listed below
Sorting:
- Verilog Repository for GIT☆35Updated 4 years ago
- ☆28Updated 7 months ago
- USB 2.0 Device IP Core☆74Updated 8 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Updated 11 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated last year
- A look ahead, round-robing parametrized arbiter written in Verilog.☆43Updated 5 years ago
- SPI-Flash XIP Interface (Verilog)☆48Updated 4 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 3 months ago
- ☆34Updated 6 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- Generic AXI master stub☆19Updated 11 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Updated 5 years ago
- ☆23Updated 6 years ago
- UART -> AXI Bridge☆70Updated 4 years ago
- Xilinx IP repository☆13Updated 7 years ago
- USB -> AXI Debug Bridge☆42Updated 4 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- Testbenches for HDL projects☆22Updated this week
- Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý.☆13Updated 4 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 5 years ago
- UART 16550 core☆38Updated 11 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19Updated 7 years ago
- ☆20Updated 3 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Updated 6 years ago
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago