Alternatives and similar repositories for xv6-riscv

Users that are interested in xv6-riscv are comparing it to the libraries listed below

• starfive-tech / u-boot
  ☆50Updated 3 months ago
• riscv-non-isa / riscv-server-platform
  The RISC-V Server Platform specification defines a standardized set of hardware and sofware capabilities, that portable system software, …
  ☆22Updated 3 weeks ago
• starfive-tech / opensbi
  ☆18Updated 3 months ago
• jevinskie / riscv-smol-linux-kernel
  Patched sources/configs for RISC-V Linux with musl-based toolchain targeting 8 MB RAM
  ☆24Updated 3 years ago
• starfive-tech / Fedora_on_StarFive
  ☆63Updated 2 years ago
• westerndigitalcorporation / RISC-V-Linux
  This repository provides a Linux kernel bootable on RISC-V boards from SiFive
  ☆170Updated 5 years ago
• riscv-non-isa / riscv-brs
  The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSV…
  ☆58Updated last month
• martinKindall / xv6-rv32
  Port of MIT's xv6 OS to 32 bit RISC V
  ☆12Updated 2 years ago
• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆25Updated 4 years ago
• ylyamin / RT-Thread-on-Allwinner-D1H
  Experimentation with the RT-Thread Operating System with the Allwinner D1H
  ☆12Updated last year
• tommythorn / tinytapeout-4-bit-cpu
  A design for TinyTapeout
  ☆18Updated 3 years ago
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆58Updated 2 years ago
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆48Updated 3 years ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆61Updated 5 years ago
• michaelengel / xv6-rv32
  Port of MIT's xv6 OS to 32 bit RISC V
  ☆44Updated 3 years ago
• rtfb / riscv-hobby-os
  ☆29Updated last year
• machdyne / kakao
  Kakao Linux
  ☆39Updated 8 months ago
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆50Updated last year
• redstar / llvm-m88k
  LLVM backend for m88k architecture
  ☆51Updated 5 months ago
• popovicu / linux-no-mmu-userspace-example
  ☆45Updated 2 years ago
• michaelengel / xv6-vf2
  Port of the xv6 OS to the VisionFive 2 RISC V board
  ☆22Updated 2 years ago
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆223Updated last year
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 9 months ago
• franzflasch / riscv_em
  Simple risc-v emulator, able to run linux, written in C.
  ☆147Updated last year
• sifiveinc / meta-sifive
  SiFive OpenEmbedded / Yocto BSP Layer
  ☆54Updated last week
• noteed / riscv-hello-asm
  Bare metal RISC-V assembly hello world
  ☆63Updated 4 years ago
• nand2mario / 486tang
  80486 on the Sipeed Tang Console 138K FPGA
  ☆96Updated last month
• howerj / bit-serial
  A bit-serial CPU written in VHDL, with a simulator written in C.
  ☆135Updated last year
• Forty-Bot / ethernet
  WIP 100BASE-TX PHY
  ☆77Updated last year
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago