nishthaparashar / Floating-Point-ALU-in-VerilogLinks
32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
☆90Updated 6 years ago
Alternatives and similar repositories for Floating-Point-ALU-in-Verilog
Users that are interested in Floating-Point-ALU-in-Verilog are comparing it to the libraries listed below
Sorting:
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- An AXI4 crossbar implementation in SystemVerilog☆174Updated 2 weeks ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆175Updated 9 months ago
- Network on Chip Implementation written in SytemVerilog☆191Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- AXI DMA 32 / 64 bits☆120Updated 11 years ago
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- A Fast, Low-Overhead On-chip Network☆224Updated last month
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆78Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated last year
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆79Updated 7 years ago
- round robin arbiter☆75Updated 11 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- Implementing Different Adder Structures in Verilog☆72Updated 6 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆134Updated 5 years ago
- IC implementation of TPU☆131Updated 5 years ago
- Vector processor for RISC-V vector ISA☆126Updated 4 years ago
- IEEE 754 floating point unit in Verilog☆145Updated 9 years ago
- ☆68Updated 9 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last month
- SDRAM controller with AXI4 interface☆97Updated 6 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 8 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆47Updated last year
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆69Updated 8 months ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- 3×3脉动阵列乘法器☆47Updated 5 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆184Updated 5 years ago