32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
☆100Apr 30, 2019Updated 6 years ago
Alternatives and similar repositories for Floating-Point-ALU-in-Verilog
Users that are interested in Floating-Point-ALU-in-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Gate level Implementation of floating point arithmetic as per IEEE 754☆11May 18, 2021Updated 4 years ago
- Verilog Code for an 8-bit ALU☆15Oct 29, 2016Updated 9 years ago
- Verilog Implementation of 32-bit Floating Point Adder☆48May 4, 2020Updated 5 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- Design for 4 x 4 Matrix Multiplication using Verilog☆35Jun 9, 2015Updated 10 years ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Jan 12, 2021Updated 5 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- Alibaba Cloud AS02MC04 hack☆43Mar 28, 2026Updated 2 weeks ago
- Single Instruction Multiple Threads GPU Core with textbook Streaming Multi-Processor features☆61Jan 30, 2026Updated 2 months ago
- synthesiseable ieee 754 floating point library in verilog☆726Mar 13, 2023Updated 3 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆32Mar 13, 2025Updated last year
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆146Jul 17, 2022Updated 3 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆152Feb 11, 2025Updated last year
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆69Aug 10, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- 32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their intern…☆27May 1, 2018Updated 7 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- Stencil with Optimized Dataflow Architecture☆18Feb 27, 2024Updated 2 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- A small Neural Network Processor for Edge devices.☆18Nov 22, 2022Updated 3 years ago
- 使用Verilog设计的带四舍五入功能的浮点加法器☆22Dec 19, 2011Updated 14 years ago
- 16QAM modulation and demodulation by Verilog☆22Jan 4, 2021Updated 5 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 7 years ago
- A survey on architectural simulators focused on CPU caches.☆16Feb 8, 2020Updated 6 years ago
- NordVPN Threat Protection Pro™ • AdTake your cybersecurity to the next level. Block phishing, malware, trackers, and ads. Lightweight app that works with all browsers.
- Basic floating-point components for RISC-V processors☆12Aug 13, 2017Updated 8 years ago
- ☆17Mar 8, 2025Updated last year
- 2D Systolic Array Multiplier☆26Jan 27, 2024Updated 2 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago
- LSTM neural network (verilog)☆15Dec 5, 2018Updated 7 years ago
- Switched SRAM-based Multi-ported RAM☆19Nov 10, 2024Updated last year
- Pipelined MIPS architecture created in Verilog. Includes data forwarding and hazard detection.☆16Apr 1, 2018Updated 8 years ago
- SoCRocket - Core Repository☆38Mar 6, 2017Updated 9 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 12 years ago
- IEEE 754 floating point unit in Verilog☆149May 20, 2016Updated 9 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆164May 10, 2025Updated 11 months ago
- 32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog☆18Aug 27, 2020Updated 5 years ago
- Classify modulation of signals☆16Jan 16, 2020Updated 6 years ago
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆25Jun 5, 2018Updated 7 years ago
- ☆14Feb 24, 2025Updated last year