32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
☆102Apr 30, 2019Updated 7 years ago
Alternatives and similar repositories for Floating-Point-ALU-in-Verilog
Users that are interested in Floating-Point-ALU-in-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Gate level Implementation of floating point arithmetic as per IEEE 754☆11May 18, 2021Updated 5 years ago
- Verilog Code for an 8-bit ALU☆15Oct 29, 2016Updated 9 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆35Jan 12, 2021Updated 5 years ago
- Design for 4 x 4 Matrix Multiplication using Verilog☆33Jun 9, 2015Updated 11 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Verilog Implementation of 32-bit Floating Point Adder☆49May 4, 2020Updated 6 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆33Mar 13, 2025Updated last year
- synthesiseable ieee 754 floating point library in verilog☆745Mar 13, 2023Updated 3 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆71Aug 10, 2024Updated last year
- FPGA based Vision Transformer accelerator (Harvard CS205)☆160Feb 11, 2025Updated last year
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆154Jul 17, 2022Updated 4 years ago
- RTL implementation of a ray-tracing GPU☆16Dec 18, 2012Updated 13 years ago
- 16QAM modulation and demodulation by Verilog☆20Jan 4, 2021Updated 5 years ago
- Stencil with Optimized Dataflow Architecture☆18Feb 27, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- 使用Verilog设计的带四舍五入功能的浮点加法器☆22Dec 19, 2011Updated 14 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 8 years ago
- A survey on architectural simulators focused on CPU caches.☆16Feb 8, 2020Updated 6 years ago
- Basic floating-point components for RISC-V processors☆12Aug 13, 2017Updated 8 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆15Jan 4, 2019Updated 7 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 12 years ago
- LSTM neural network (verilog)☆16Dec 5, 2018Updated 7 years ago
- A small Neural Network Processor for Edge devices.☆20Nov 22, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Pipelined MIPS architecture created in Verilog. Includes data forwarding and hazard detection.☆16Apr 1, 2018Updated 8 years ago
- Switched SRAM-based Multi-ported RAM☆19Nov 10, 2024Updated last year
- SoCRocket - Core Repository☆39Mar 6, 2017Updated 9 years ago
- ☆386Jun 14, 2026Updated last month
- 2D Systolic Array Multiplier☆35Updated this week
- IEEE 754 floating point unit in Verilog☆151May 20, 2016Updated 10 years ago
- Classify modulation of signals☆16Jan 16, 2020Updated 6 years ago
- 32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog☆18Aug 27, 2020Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆174May 10, 2025Updated last year
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- ☆14Updated this week
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 13 years ago
- Basic floating-point components for RISC-V processors☆69Dec 4, 2019Updated 6 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 9 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 5 months ago
- ☆15Sep 29, 2021Updated 4 years ago