Alternatives and similar repositories for Floating-Point-ALU-in-Verilog

Users that are interested in Floating-Point-ALU-in-Verilog are comparing it to the libraries listed below

• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆156Updated 3 weeks ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆75Updated last year
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆73Updated 7 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆103Updated 4 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆114Updated 10 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆97Updated 5 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆125Updated 7 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆205Updated 2 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆207Updated this week
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆94Updated 5 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆166Updated 6 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆65Updated 5 months ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆160Updated 5 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆246Updated 7 months ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆64Updated 9 months ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆152Updated 11 months ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆54Updated 4 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆45Updated 5 years ago
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆137Updated 9 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆72Updated 3 years ago
• ForrestBlue / cortexm0ds
  ☆64Updated 9 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆88Updated 3 years ago
• kuladeepsaireddy / OpenNoc
  ☆33Updated 6 years ago
• djtfoo / lenet5-verilog
  A Verilog design of LeNet-5, a Convolutional Neural Network architecture
  ☆33Updated 4 years ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆59Updated 3 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆117Updated 6 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆74Updated 10 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆117Updated 3 weeks ago