nishthaparashar / Floating-Point-ALU-in-Verilog
32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
☆79Updated 5 years ago
Alternatives and similar repositories for Floating-Point-ALU-in-Verilog:
Users that are interested in Floating-Point-ALU-in-Verilog are comparing it to the libraries listed below
- An AXI4 crossbar implementation in SystemVerilog☆131Updated 2 months ago
- AXI DMA 32 / 64 bits☆106Updated 10 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 6 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆88Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆66Updated last year
- Some useful documents of Synopsys☆62Updated 3 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆121Updated 6 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆160Updated 3 months ago
- AXI总线连接器☆94Updated 4 years ago
- AMBA bus generator including AXI, AHB, and APB☆96Updated 3 years ago
- ☆29Updated 5 years ago
- AHB DMA 32 / 64 bits☆52Updated 10 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- A verilog implementation for Network-on-Chip☆71Updated 7 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated last month
- AXI Interconnect☆47Updated 3 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆186Updated last year
- DDR2 memory controller written in Verilog☆73Updated 12 years ago
- RTL Verilog library for various DSP modules☆84Updated 3 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆116Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- SDRAM controller with AXI4 interface☆87Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆58Updated 6 months ago
- IC implementation of Systolic Array for TPU☆189Updated 4 months ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆99Updated last month
- Network on Chip Implementation written in SytemVerilog☆167Updated 2 years ago
- 3×3脉动阵列乘法器☆37Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated this week
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆54Updated 2 years ago