Alternatives and similar repositories for ECHO-and-FIR-FILTER-implementation-on-Verilog-HDL

Users that are interested in ECHO-and-FIR-FILTER-implementation-on-Verilog-HDL are comparing it to the libraries listed below

• sujan2599 / LMS-Adaptive-FIR-Filter
  design of LMS adaptive 4-tap FIR filter using Distributed Arithmetic architecture in verilog
  ☆10Updated 3 years ago
• AbdullahAnsarii / BandPassFilter
  FIR band-pass filter using Verilog HDL.
  ☆12Updated 5 years ago
• maxs-well / FIR_Implementation
  FIR filter implementation
  ☆29Updated 5 years ago
• uestcXJW / FIR_Filter
  A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB
  ☆10Updated 5 years ago
• edwardclin2003 / LowPassFilterImageFPGA
  Verilog code that does 2D Low Pass Filter on a greyscale image
  ☆10Updated 10 years ago
• Digilent / Zedboard-DMA
  ☆13Updated 6 years ago
• ivanvig / 2dconv-FPGA
  A 2D convolution hardware implementation written in Verilog
  ☆50Updated 4 years ago
• mnmhdanas / DA-Based-LMS-Adaptive-filter
  Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…
  ☆16Updated 4 years ago
• fengyulin1996 / Verilog-DSP
  FIR，FFT based on Verilog
  ☆13Updated 7 years ago
• yaseensalah / Digital-Design-of-FIR-Filter
  Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Veril…
  ☆28Updated 2 years ago
• DexWen / LMS-Adaptive-filter
  LMS-Adaptive Filter implement using verilog and Matlab
  ☆47Updated 9 years ago
• ykqiu / image-processing
  Real-Time Image Processing for ASIC/FGPA
  ☆20Updated 3 years ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆22Updated 7 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 11 years ago
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆36Updated 5 years ago
• Reenforcements / VerilogDE2115AudioFilters
  Student project for using audio on the DE2-115 FPGA development board.
  ☆27Updated 7 years ago
• nour176yj / FIR-LPF-Digital-Design-
  A 66-order (67 taps) hamming FIR LPF Filter is to be designed with a cutoff frequency of 200 KHZ for a sampling frequency of 1 MHZ
  ☆14Updated 2 years ago
• AugustinJose1221 / FFTx32
  A 32 point radix-2 FFT module written in Verilog
  ☆23Updated 5 years ago
• xfguo / spi
  SPI Master Core clone from OpenCores
  ☆11Updated 12 years ago
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆48Updated last year
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆41Updated 8 years ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 7 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 11 years ago
• ajackevic / ELEC5882
  The Design and Implementation of a Pulse Compression Filter on an FPGA.
  ☆31Updated 4 years ago
• suisuisi / AXI4-Stream-FIR-filter
  AXI4-Stream FIR filter IP
  ☆19Updated 3 years ago
• ncos / Xilinx-Verilog
  Zedboard projects
  ☆11Updated 9 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆26Updated 4 years ago
• Divyansh03 / FIR-Filter-in-Verilog
  FIR Filter in Verilog
  ☆15Updated 6 years ago
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆37Updated 4 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago