An UVM example of UART
☆20Aug 31, 2020Updated 5 years ago
Alternatives and similar repositories for UVM_UART_Example
Users that are interested in UVM_UART_Example are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog UVM testbench example☆37May 8, 2024Updated last year
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Jun 5, 2017Updated 8 years ago
- General Purpose I/O agent written in UVM☆18Jun 29, 2017Updated 8 years ago
- This script builds the UVM register model, based on pre-defined address map in markdown (mk) style☆12Mar 23, 2018Updated 8 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆159Mar 31, 2020Updated 5 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆39Jun 24, 2020Updated 5 years ago
- ☆11May 31, 2016Updated 9 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆60Aug 9, 2020Updated 5 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆106Jul 2, 2023Updated 2 years ago
- CORE-V MCU UVM Environment and Test Bench☆26Jul 19, 2024Updated last year
- UART design in SV and verification using UVM and SV☆53Nov 30, 2019Updated 6 years ago
- UVM testbench for verifying the Pulpino SoC☆12Mar 23, 2020Updated 6 years ago
- An uvm verification env for ahb2apb bridge☆57Apr 9, 2021Updated 4 years ago
- UVM interactive debug library☆35Feb 28, 2026Updated 3 weeks ago
- Simple template-based UVM code generator☆29Jan 4, 2023Updated 3 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆31Mar 23, 2024Updated last year
- UVM Testbench to verify serial transmission of data between SPI master and slave☆53Jul 4, 2020Updated 5 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆48Jun 19, 2020Updated 5 years ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆42Jul 11, 2025Updated 8 months ago
- 为了学习UVM验证相关知识，需要动手尝试实际的项目。作为一个初学者，难以接触到实际的项目，于是我从夏宇闻老师的《Verilog数字系统设计教程》一书中，挑选出一个简单的小设计，作为我的验证对象，并围绕它编写了UVM验证环境。☆24Oct 9, 2020Updated 5 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆13Oct 26, 2019Updated 6 years ago
- FPGA Low latency 10GBASE-R PCS☆12May 23, 2023Updated 2 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Aug 28, 2023Updated 2 years ago
- DOULOS Easier UVM Code Generator☆39May 6, 2017Updated 8 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆64Oct 19, 2023Updated 2 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆36Feb 6, 2019Updated 7 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆19Sep 14, 2023Updated 2 years ago
- SKY130 SRAM macros generated by SRAM 22☆19Aug 19, 2025Updated 7 months ago
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆14Sep 17, 2019Updated 6 years ago
- 开放验证平台NutShell Cache验证案例☆11Dec 2, 2025Updated 3 months ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆50Mar 3, 2024Updated 2 years ago
- ahb scram controller, design and verification☆28Jun 20, 2018Updated 7 years ago
- AMBA 3 AHB UVM TB☆35Mar 21, 2019Updated 7 years ago
- UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…☆15Dec 23, 2024Updated last year
- A complete UVM verification testbench for FIFO☆13Mar 21, 2016Updated 10 years ago
- A Verilog implementation of a processor cache.☆37Dec 29, 2017Updated 8 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆119Dec 29, 2024Updated last year
- An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) at UMJI.☆11Dec 28, 2020Updated 5 years ago
- UCSD CSE240A Project: Branch Predictor☆11Jul 24, 2017Updated 8 years ago