Alternatives and similar repositories for softex

Users that are interested in softex are comparing it to the libraries listed below

• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆66Updated 5 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆64Updated 2 weeks ago
• pulp-platform / fpu
  ☆56Updated 6 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆96Updated last week
• pulp-platform / ITA
  ☆54Updated 6 months ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 4 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆81Updated 2 years ago
• kuladeepsaireddy / OpenNoc
  ☆37Updated 6 years ago
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆35Updated 2 weeks ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆70Updated 6 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆27Updated 6 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆59Updated last week
• pulp-platform / quadrilatero
  matrix-coprocessor for RISC-V
  ☆25Updated 6 months ago
• VeriGOOD-ML / public
  ☆63Updated 6 months ago
• gnodipac886 / ViT-FPGA-TPU
  FPGA based Vision Transformer accelerator (Harvard CS205)
  ☆137Updated 8 months ago
• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆35Updated last week
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Updated 4 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆62Updated 4 months ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆69Updated last year
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆68Updated last week
• chrisneuf / Deep-Neural-Network-Hardware-Accelerator
  My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket
  ☆26Updated 6 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆36Updated 3 years ago
• Nikola2444 / RISC-V-vector-processor
  ☆15Updated 3 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆57Updated 3 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆105Updated 5 years ago
• gem5-X / TiC-SAT
  ☆17Updated 5 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆82Updated 4 years ago
• FedericoSerafini / HLS-CNN
  High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
  ☆41Updated last year