☆15Oct 20, 2025Updated 4 months ago
Alternatives and similar repositories for softex
Users that are interested in softex are comparing it to the libraries listed below
Sorting:
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- ☆46Apr 8, 2023Updated 2 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33May 26, 2024Updated last year
- A simple, scalable, source-synchronous, all-digital DDR link☆36Dec 8, 2025Updated 2 months ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Jan 12, 2021Updated 5 years ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 4 years ago
- Reinforcement learning with 2D games☆16May 16, 2025Updated 9 months ago
- RADIX-4 SRT division☆12Oct 31, 2019Updated 6 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- JPEG编解码从零开始实现(python JPEG codec)☆10Jul 29, 2022Updated 3 years ago
- ☆10Jun 4, 2024Updated last year
- 基于Xilinx FPGA的通用型 CNN卷积神经网络加速器,本设计基于KV260板卡,MpSoC架构均可移植☆18Dec 13, 2024Updated last year
- FSA: Fusing FlashAttention within a Single Systolic Array☆89Aug 12, 2025Updated 6 months ago
- Basic floating-point components for RISC-V processors☆11Aug 13, 2017Updated 8 years ago
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆14Feb 16, 2024Updated 2 years ago
- 基于FPGA-Pynq的车牌识别系统。The LPR system of FPGA-Pynq☆13Mar 22, 2019Updated 6 years ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆11May 2, 2022Updated 3 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 3 months ago
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jan 7, 2026Updated last month
- This project implements the Titans architecture from the paper "Titans: Learning to Memorize at Test Time" for market data prediction.☆11Jan 19, 2025Updated last year
- ☆18May 5, 2022Updated 3 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆13May 9, 2022Updated 3 years ago
- Porting FreeRTOS to a RISC-V based system on PYNQ-Z2☆11Dec 26, 2024Updated last year
- C library containing high resolution timer implementation for several platforms.☆10Oct 20, 2020Updated 5 years ago
- Compile & Run Quantum Intermediate Representation (QIR) Programs on Rigetti Quantum Cloud Services (QCS)☆12Oct 1, 2025Updated 4 months ago
- A PyTorch implementation of [VCT](https://github.com/google-research/google-research/tree/master/vct)☆10Nov 25, 2022Updated 3 years ago
- Matrix multiplication accelerator on ZYNQ SoC.☆12Apr 29, 2025Updated 10 months ago
- connect your raspberry PI via SSH on your Android smartphone☆13Feb 24, 2021Updated 5 years ago
- FocusFlow: Boosting Key-Points Optical Flow Estimation for Autonomous Driving☆10Jan 22, 2024Updated 2 years ago
- Fritzing parts for most common DIP ICs including 74LS Series and more, which is used in Digital Electronics or Logic Circuit and Design.☆19Jul 18, 2024Updated last year
- spike-vp☆12Feb 5, 2024Updated 2 years ago
- Simodense: a RISC-V softcore for custom SIMD instructions☆17Feb 16, 2026Updated last week
- A generic Janus WebRTC Media Server Docker container☆12Mar 15, 2024Updated last year
- The official repository of Quamba1 [ICLR 2025] & Quamba2 [ICML 2025]☆67Jun 19, 2025Updated 8 months ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- Appunti laurea magistrale in Ingegeria Informatica☆14Dec 21, 2022Updated 3 years ago
- ☆16Aug 14, 2025Updated 6 months ago
- This repository contains papers for a comprehensive survey on accelerated generation techniques in Large Language Models (LLMs).☆11May 24, 2024Updated last year
- This repo is to inplemente the riscv soc on the xilinx pynq-z2 board☆12Dec 6, 2023Updated 2 years ago