Alternatives and similar repositories for softex

Users that are interested in softex are comparing it to the libraries listed below

• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆70Updated 5 years ago
• pulp-platform / ITA
  ☆57Updated 7 months ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆66Updated 3 weeks ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆97Updated 3 weeks ago
• Xilinx / xup_high_level_synthesis_design_flow
  AMD University Program HLS tutorial
  ☆119Updated last year
• pulp-platform / quadrilatero
  matrix-coprocessor for RISC-V
  ☆25Updated 7 months ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆82Updated 2 years ago
• kuladeepsaireddy / OpenNoc
  ☆37Updated 6 years ago
• pulp-platform / fpu
  ☆57Updated 6 years ago
• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆38Updated last month
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆35Updated last month
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆37Updated 4 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆29Updated 6 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• VeriGOOD-ML / public
  ☆64Updated 7 months ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆59Updated last week
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆93Updated 3 weeks ago
• pulp-platform / fpu_ss
  CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor
  ☆12Updated 2 weeks ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆71Updated last year
• gem5-X / TiC-SAT
  ☆19Updated 6 months ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆25Updated 4 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆70Updated 5 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆71Updated 6 years ago
• Nikola2444 / RISC-V-vector-processor
  ☆15Updated 3 years ago
• x-heep / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆224Updated last week
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆26Updated 2 weeks ago
• FedericoSerafini / HLS-CNN
  High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
  ☆41Updated last year
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆204Updated 5 years ago
• riscv-stc / riscv-matrix-project
  Top project for RISC-V Matrix extension proposal and related opensource implementations.
  ☆35Updated last year