ericgineer / CICLinks
A CIC filter implemented in Verilog
☆25Updated 10 years ago
Alternatives and similar repositories for CIC
Users that are interested in CIC are comparing it to the libraries listed below
Sorting:
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- USB Full Speed PHY☆48Updated 5 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- DSP WishBone Compatible Cores☆14Updated 11 years ago
- Audio filtering with pyfda and cocotb☆12Updated 5 years ago
- MMC (and derivative standards) host controller☆25Updated 5 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆40Updated last year
- Fork of OpenCores jpegencode with Cocotb testbench☆45Updated 10 years ago
- A current mode buck converter on the SKY130 PDK☆34Updated 4 years ago
- Verilog Repository for GIT☆35Updated 4 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- Wishbone interconnect utilities☆44Updated last month
- Verification IP project for I3C protocol☆23Updated 11 months ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- USB -> AXI Debug Bridge☆42Updated 4 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆39Updated 7 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- ☆30Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆82Updated 3 years ago
- ☆28Updated last month
- Drive a Wishbone master bus with an SPI bus.☆10Updated 9 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Updated 3 years ago
- TCP/IP controlled VPI JTAG Interface.☆69Updated last year
- Universal Advanced JTAG Debug Interface☆17Updated last year
- HW JPEG decoder wrapper with AXI-4 DMA☆37Updated 5 years ago
- ☆28Updated 4 years ago