A CIC filter implemented in Verilog
☆24Sep 7, 2015Updated 10 years ago
Alternatives and similar repositories for CIC
Users that are interested in CIC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)☆33Aug 14, 2020Updated 5 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago
- Verilog Language Extension for Visual Studio☆20Jan 14, 2026Updated 3 months ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- FIR filter implementation☆29Mar 19, 2020Updated 6 years ago
- HDMI + GPU-pipeline + FFT☆14Mar 4, 2016Updated 10 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- 关于CIC滤波器、ISOP补偿器、HB滤波器的相关Matlab仿真与FPGA工程☆15Dec 25, 2023Updated 2 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Feb 25, 2019Updated 7 years ago
- Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic☆32May 6, 2017Updated 8 years ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 8 years ago
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆12Apr 19, 2022Updated 4 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆32Aug 31, 2020Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- STM32G474 USB CDC example implementation, combined with Jan Breuer's SCPI parser library v2☆35Jan 4, 2023Updated 3 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Open source/hardware SoC plattform based on the lattice mico 32 softcore☆15Apr 10, 2010Updated 16 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- RTL to GDS via Cadence Tools☆17May 17, 2022Updated 3 years ago
- FIR implemention with Verilog☆50May 18, 2019Updated 6 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Deploying Haskell to Lattice iCE40 using fully open source toolchain☆14May 22, 2016Updated 9 years ago
- Somewhere to put the esp32 code I am playing with.☆14Jan 24, 2016Updated 10 years ago
- LMS sound filtering by Verilog☆43Apr 5, 2020Updated 6 years ago
- ☆28Feb 5, 2020Updated 6 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆50Oct 21, 2016Updated 9 years ago
- bpm.is sauce☆10Nov 5, 2021Updated 4 years ago
- Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Veril…☆30Mar 4, 2023Updated 3 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆20Apr 16, 2026Updated 2 weeks ago
- HDL components to build a customized Wishbone crossbar switch☆15May 30, 2019Updated 6 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆21Mar 9, 2021Updated 5 years ago
- This project demonstrates DSP capabilities of Terasic DE2-115☆28Jun 22, 2018Updated 7 years ago
- GNURadio implementation of the lazy Viterbi algorithm☆13May 8, 2020Updated 5 years ago
- FPGA Portable Music Generator☆11Aug 1, 2018Updated 7 years ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆25May 13, 2023Updated 2 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆110Jul 2, 2023Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆113Feb 22, 2024Updated 2 years ago