A CIC filter implemented in Verilog
☆25Sep 7, 2015Updated 10 years ago
Alternatives and similar repositories for CIC
Users that are interested in CIC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)☆33Aug 14, 2020Updated 5 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆11Aug 15, 2020Updated 5 years ago
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆26May 12, 2020Updated 6 years ago
- Verilog Language Extension for Visual Studio☆20Jun 26, 2026Updated last week
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- FIR filter implementation☆29Mar 19, 2020Updated 6 years ago
- HDMI + GPU-pipeline + FFT☆14Mar 4, 2016Updated 10 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Feb 25, 2019Updated 7 years ago
- Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic☆32May 6, 2017Updated 9 years ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 8 years ago
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆12Apr 19, 2022Updated 4 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆33Aug 31, 2020Updated 5 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Open source/hardware SoC plattform based on the lattice mico 32 softcore☆15Apr 10, 2010Updated 16 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Linux SPI protocol device driver for Lattice ECP5 FPGA programming through slave SPI interface☆10Apr 10, 2023Updated 3 years ago
- FIR implemention with Verilog☆50May 18, 2019Updated 7 years ago
- RTL to GDS via Cadence Tools☆19May 17, 2022Updated 4 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- Deploying Haskell to Lattice iCE40 using fully open source toolchain☆14May 22, 2016Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- LMS sound filtering by Verilog☆43Apr 5, 2020Updated 6 years ago
- ☆28Feb 5, 2020Updated 6 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆50Oct 21, 2016Updated 9 years ago
- official build specifications for jupyter☆13Jun 3, 2021Updated 5 years ago
- bpm.is sauce☆10Nov 5, 2021Updated 4 years ago
- Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Veril…☆31Mar 4, 2023Updated 3 years ago
- ☆21Mar 9, 2021Updated 5 years ago
- HDL components to build a customized Wishbone crossbar switch☆15May 30, 2019Updated 7 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆21May 29, 2026Updated last month
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- HiLoTOF -- Hardware-in-the-Loop Test framework for Open FPGAs☆13Feb 9, 2019Updated 7 years ago
- GNURadio implementation of the lazy Viterbi algorithm☆13May 8, 2020Updated 6 years ago
- FPGA Portable Music Generator☆11Aug 1, 2018Updated 7 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆115Jul 2, 2023Updated 3 years ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆26May 13, 2023Updated 3 years ago
- Virtual SoapySDR driver for sharing a single physical device via shared memory☆20Mar 15, 2026Updated 3 months ago
- Implementation of Sobel Filter in Verilog☆28Mar 10, 2017Updated 9 years ago