ericgineer / CICLinks
A CIC filter implemented in Verilog
☆24Updated 10 years ago
Alternatives and similar repositories for CIC
Users that are interested in CIC are comparing it to the libraries listed below
Sorting:
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆38Updated last year
- Verilog Repository for GIT☆35Updated 4 years ago
- DSP WishBone Compatible Cores☆14Updated 11 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆21Updated 11 months ago
- USB -> AXI Debug Bridge☆41Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- Wishbone interconnect utilities☆44Updated last month
- Extensible FPGA control platform☆61Updated 2 years ago
- A current mode buck converter on the SKY130 PDK☆34Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- Verification IP project for I3C protocol☆21Updated 10 months ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 11 months ago
- TCP/IP controlled VPI JTAG Interface.☆69Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆35Updated 11 months ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- Flip flop setup, hold & metastability explorer tool☆52Updated 3 years ago
- MMC (and derivative standards) host controller☆25Updated 5 years ago
- A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board☆12Updated 7 years ago
- Audio filtering with pyfda and cocotb☆12Updated 5 years ago
- USB Full Speed PHY☆48Updated 5 years ago
- Time to Digital Converter (TDC)☆36Updated 5 years ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- SERDES-based TDC core for Spartan-6☆18Updated 13 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Updated 5 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago