ericgineer / CICLinks
A CIC filter implemented in Verilog
☆22Updated 9 years ago
Alternatives and similar repositories for CIC
Users that are interested in CIC are comparing it to the libraries listed below
Sorting:
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- ☆26Updated last year
- USB Full Speed PHY☆44Updated 5 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 5 years ago
- USB -> AXI Debug Bridge☆39Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Wishbone interconnect utilities☆41Updated 3 months ago
- SERDES-based TDC core for Spartan-6☆18Updated 12 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆26Updated 3 months ago
- USB 1.1 Host and Function IP core☆23Updated 10 years ago
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆11Updated this week
- IP Cores that can be used within Vivado☆26Updated 4 years ago
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- UART models for cocotb☆29Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- SPI-Flash XIP Interface (Verilog)☆38Updated 3 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 4 months ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- ☆21Updated last month
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Video Stream Scaler☆40Updated 10 years ago
- ☆30Updated 4 years ago