Alternatives and similar repositories for DC_script:

Users that are interested in DC_script are comparing it to the libraries listed below

• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆16Updated 3 years ago
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆22Updated 3 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆39Updated 3 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆96Updated 4 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆73Updated 7 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆54Updated 10 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆93Updated 4 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆60Updated 7 months ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆43Updated 5 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆52Updated 3 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆109Updated 10 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆90Updated 3 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆34Updated 2 years ago
• KafCoppelia / uvm-mcdf
  Mirror of william_william/uvm-mcdf on Gitee
  ☆21Updated 2 years ago
• Verdvana / AXI_SRAM
  支持AXI总线协议的8k×8 SP SRAM
  ☆25Updated 4 years ago
• chengquan / IC_FLOW
  ☆15Updated last year
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆14Updated 10 months ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆73Updated 7 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆147Updated 5 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆82Updated 5 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆54Updated last month
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆58Updated last year
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆11Updated 4 years ago
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆41Updated 7 months ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆70Updated last year
• mfkiwl / E203_dma
  ☆9Updated 4 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆40Updated 4 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆29Updated 4 years ago