16-bit Adder Multiplier hardware on Digilent Basys 3
☆84Aug 3, 2023Updated 3 years ago
Alternatives and similar repositories for Fixed-Floating-Point-Adder-Multiplier
Users that are interested in Fixed-Floating-Point-Adder-Multiplier are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Implementation of 32-bit Floating Point Adder☆50May 4, 2020Updated 6 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆125Apr 3, 2026Updated 6 months ago
- STONNE Simulator integrated into SST Simulator☆22Apr 5, 2024Updated 2 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- A simulation framework for modeling efficiency of Graph Neural Network Dataflows☆24Feb 14, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 7 years ago
- 32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their intern…☆27May 1, 2018Updated 8 years ago
- Adaptive floating-point based numerical format for resilient deep learning☆14Apr 11, 2022Updated 4 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆125Jan 26, 2013Updated 13 years ago
- IEEE 754 floating point unit in Verilog☆153May 20, 2016Updated 10 years ago
- 使用Verilog设计的带四舍五入功能的浮点加法器☆22Dec 19, 2011Updated 14 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆22May 4, 2017Updated 9 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 7 years ago
- ASIC Design kit for Skywater 130 for use with mflowgen☆16Mar 12, 2023Updated 3 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆77Aug 13, 2024Updated 2 years ago
- HDMI + GPU-pipeline + FFT☆15Mar 4, 2016Updated 10 years ago
- ☆22Jan 9, 2024Updated 2 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆52Jul 4, 2019Updated 7 years ago
- ☆14Apr 8, 2025Updated last year
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆37Jan 12, 2021Updated 5 years ago
- This repository contains papers for a comprehensive survey on accelerated generation techniques in Large Language Models (LLMs).☆11May 24, 2024Updated 2 years ago
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators☆11Apr 9, 2019Updated 7 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- RTL generator for SpGEMM☆13Feb 2, 2021Updated 5 years ago
- Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim☆14May 8, 2021Updated 5 years ago
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 4 years ago
- BYU Pynq PR Video Pipeline Hardware☆12Oct 2, 2025Updated last year
- Parameterized Booth Multiplier in Verilog 2001☆52Oct 30, 2022Updated 3 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆35Aug 31, 2020Updated 6 years ago
- Provides automation scripts for building BFMs☆16Apr 19, 2025Updated last year
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- 文档编写☆14Sep 19, 2020Updated 6 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆62Nov 22, 2023Updated 2 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆28Jan 11, 2019Updated 7 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆130Dec 15, 2021Updated 4 years ago
- Verilog program☆16Jul 27, 2020Updated 6 years ago
- To design test bench of the APB protocol☆21Dec 30, 2020Updated 5 years ago
- This is the final project for the BP NN FPGA implementation☆11Jan 14, 2017Updated 9 years ago
- The template for VLSI project☆29Mar 3, 2023Updated 3 years ago