16-bit Adder Multiplier hardware on Digilent Basys 3
☆84Aug 3, 2023Updated 2 years ago
Alternatives and similar repositories for Fixed-Floating-Point-Adder-Multiplier
Users that are interested in Fixed-Floating-Point-Adder-Multiplier are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Implementation of 32-bit Floating Point Adder☆49May 4, 2020Updated 6 years ago
- A simulation framework for modeling efficiency of Graph Neural Network Dataflows☆24Feb 14, 2025Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆123Apr 3, 2026Updated 2 months ago
- STONNE Simulator integrated into SST Simulator☆22Apr 5, 2024Updated 2 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆35Jan 12, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 7 years ago
- 32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their intern…☆27May 1, 2018Updated 8 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆123Jan 26, 2013Updated 13 years ago
- Adaptive floating-point based numerical format for resilient deep learning☆14Apr 11, 2022Updated 4 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆76Aug 13, 2024Updated last year
- IEEE 754 floating point unit in Verilog☆150May 20, 2016Updated 10 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆22May 4, 2017Updated 9 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- 使用Verilog设计的带四舍五入功能的浮点加法器☆22Dec 19, 2011Updated 14 years ago
- ASIC Design kit for Skywater 130 for use with mflowgen☆15Mar 12, 2023Updated 3 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- ☆22Jan 9, 2024Updated 2 years ago
- HDMI + GPU-pipeline + FFT☆14Mar 4, 2016Updated 10 years ago
- ☆14Apr 8, 2025Updated last year
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- RTL generator for SpGEMM☆10Feb 2, 2021Updated 5 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆50Jul 4, 2019Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 3 years ago
- BYU Pynq PR Video Pipeline Hardware☆13Oct 2, 2025Updated 8 months ago
- Parameterized Booth Multiplier in Verilog 2001☆51Oct 30, 2022Updated 3 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆33Aug 31, 2020Updated 5 years ago
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics…☆10Jul 27, 2020Updated 5 years ago
- Provides automation scripts for building BFMs☆16Apr 19, 2025Updated last year
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆27Jan 11, 2019Updated 7 years ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆21Nov 17, 2024Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- This is the final project for the BP NN FPGA implementation☆11Jan 14, 2017Updated 9 years ago
- ☆30Dec 12, 2022Updated 3 years ago
- Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim☆13May 8, 2021Updated 5 years ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- ☆14May 15, 2023Updated 3 years ago
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆35Oct 23, 2023Updated 2 years ago
- ☆63Feb 18, 2019Updated 7 years ago