ahirsharan / 32-Bit-Floating-Point-AdderLinks
Verilog Implementation of 32-bit Floating Point Adder
☆40Updated 5 years ago
Alternatives and similar repositories for 32-Bit-Floating-Point-Adder
Users that are interested in 32-Bit-Floating-Point-Adder are comparing it to the libraries listed below
Sorting:
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago
- Verilog implementation of Softmax function☆67Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆78Updated 2 years ago
- ☆35Updated 6 years ago
- ☆66Updated 6 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- A systolic array matrix multiplier☆25Updated 6 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆57Updated 11 months ago
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last month
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆53Updated 3 years ago
- ☆78Updated 10 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆26Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆166Updated 5 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆86Updated 3 months ago
- Library of approximate arithmetic circuits☆55Updated 3 years ago
- ☆17Updated 4 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆59Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- ☆32Updated 3 months ago
- ☆27Updated 5 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆34Updated last year
- ☆115Updated 5 years ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- ☆15Updated 5 years ago