Alternatives and similar repositories for mida

Users that are interested in mida are comparing it to the libraries listed below

• Daikon-Sun / Routing-Visualization
  Routing Visualization for Physical Design
  ☆19Updated 6 years ago
• aebeljs / VeRLPy
  VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (R…
  ☆26Updated 2 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆57Updated last year
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆38Updated 5 years ago
• andrsmllr / magic_vlsi_examples
  Some simple examples for the Magic VLSI physical chip layout tool.
  ☆30Updated 4 years ago
• EDAAC / EDAAC
  EDA Analytics Central
  ☆15Updated 2 years ago
• scale-lab / DRiLLS
  DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)
  ☆113Updated 2 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆30Updated 5 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 4 years ago
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆47Updated 2 years ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆16Updated 4 years ago
• mgraczyk / coursera-vlsicad
  Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout
  ☆12Updated 11 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆73Updated 7 years ago
• NVlabs / CircuitOps
  ☆80Updated 2 months ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆49Updated 6 months ago
• cgfandia / PathfinderAlgorithm
  Pathfinder routing algorithm practice
  ☆14Updated 8 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆28Updated last year
• khushhallchandra / Simulated-Annealing
  Simulated Annealing to minimize the wirelength
  ☆8Updated 8 years ago
• UNSAMDCI / PDK_ONC5
  Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library
  ☆33Updated 3 years ago
• YuanTingHsieh / ITDP
  Incremental Timing-Driven Placement, problem C of ICCAD contest 2015
  ☆13Updated 7 years ago
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago
• ABKGroup / PROBE3.0
  ☆44Updated last year
• asyncvlsi / SPRoute
  A parallel global router using the Galois framework
  ☆29Updated last year
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆55Updated 2 years ago
• yellekelyk / PyVerilog
  Python-based Verilog Parser (currently Netlist only)
  ☆54Updated 8 years ago
• jimwang99 / parser-for-chip-design
  A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
  ☆31Updated 9 years ago
• ckchengucsd / ILP-SAT-Detailed-Router
  ILP SAT Detailed Router
  ☆11Updated 5 years ago
• pkuzjx / eda-collection
  ☆105Updated 5 years ago
• clin99 / awesome-eda
  ☆92Updated 5 years ago