curry0622 / VLSI-Physical-Design-AutomationLinks
NTHU CS6135 VLSI Physical Design Automation (2022 Fall)
☆18Updated 3 years ago
Alternatives and similar repositories for VLSI-Physical-Design-Automation
Users that are interested in VLSI-Physical-Design-Automation are comparing it to the libraries listed below
Sorting:
- NTHU CS6135 VLSI實體設計自動化☆12Updated 3 years ago
- NTHU CS6135 VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing Floorplan Design…☆43Updated 4 months ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆13Updated 8 years ago
- Courseworks of CS6165 VLSI Physical Design Automation, NTHU.☆50Updated 5 years ago
- Power and Timing Optimization Using MBFF☆20Updated 8 months ago
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆24Updated 7 years ago
- Problem B: 3D Placement with D2D Vertical Connections☆11Updated 3 years ago
- ☆14Updated last year
- Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)☆45Updated 7 years ago
- ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.☆19Updated 2 years ago
- ☆14Updated 4 years ago
- IC Contest☆42Updated 2 years ago
- 超詳細 ICLAB 2024 Spring 修課心得 & 修課指南,含資源整理☆115Updated 9 months ago
- IC-contest 2012~2024☆22Updated last year
- 交通大學iclab 2023 fall☆44Updated last year
- ☆10Updated last year
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆54Updated last year
- ☆50Updated 2 years ago
- iccad contest 2022 problem B☆16Updated 3 years ago
- NCTU 2021 Spring Integrated Circuit Design Laboratory☆197Updated 2 years ago
- Combinational ATPG generator based on D-Algorithm☆16Updated 5 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆56Updated last year
- ☆93Updated 7 months ago
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆153Updated last year
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.☆34Updated 2 years ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆31Updated 3 years ago
- VLSI EDA Global Router☆79Updated 8 years ago
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.☆24Updated last year
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆154Updated 2 weeks ago
- Computer-Aided VLSI System Design☆23Updated last year