Alternatives and similar repositories for UHDM

Users that are interested in UHDM are comparing it to the libraries listed below

• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated last month
• alainmarcel / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…
  ☆26Updated this week
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆80Updated 8 months ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated 3 weeks ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 3 years ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆45Updated 4 years ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆52Updated last year
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆60Updated 5 months ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆82Updated 9 months ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated last year
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆37Updated 3 weeks ago
• taichi-ishitani / tue
  Useful UVM extensions
  ☆24Updated last year
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆59Updated last year
• agra-uni-bremen / crave
  Constrained random stimuli generation for C++ and SystemC
  ☆52Updated last year
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆49Updated 5 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 2 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆54Updated 3 weeks ago
• amiq-consulting / amiq_blog
  Code snippets from articles published on www.amiq.com/consulting/blog
  ☆36Updated last year
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆40Updated this week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆221Updated 3 weeks ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆34Updated 3 weeks ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆34Updated last month
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆41Updated 2 years ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆46Updated 9 months ago
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆121Updated last year
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆66Updated 5 months ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆29Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 8 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year