Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
☆18Feb 22, 2026Updated last week
Alternatives and similar repositories for UHDM
Users that are interested in UHDM are comparing it to the libraries listed below
Sorting:
- SystemVerilog wrapper over the Verilog Programming Interface (VPI)☆13Jun 3, 2025Updated 9 months ago
- Support code for DVCon 2021 paper submission☆12Mar 1, 2021Updated 5 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 4 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 10 years ago
- 🕒 Static Timing Analysis diagram renderer☆13Dec 13, 2023Updated 2 years ago
- Reflection API for SystemVerilog☆15Jun 5, 2025Updated 9 months ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆35Apr 15, 2020Updated 5 years ago
- Contains source code for sin/cos table verification using UVM☆21Mar 9, 2021Updated 4 years ago
- A mock framework for use with SVUnit☆19Jun 27, 2023Updated 2 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 5 years ago
- UVM VIP architecture generator☆20Aug 24, 2020Updated 5 years ago
- VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation,…☆34Feb 11, 2026Updated 3 weeks ago
- Useful UVM extensions☆27Jul 10, 2024Updated last year
- use pivpi to drive testbench event☆21Jul 21, 2016Updated 9 years ago
- make your verilog DUT test more smart☆22Sep 9, 2016Updated 9 years ago
- A CSV file parser, written in SystemVerilog☆27Jul 13, 2016Updated 9 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆449Feb 23, 2026Updated last week
- EDA physical synthesis optimization kit☆64Nov 13, 2023Updated 2 years ago
- svlib from http://www.verilab.com/resources/svlib/☆24Jun 2, 2020Updated 5 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…☆26Updated this week
- YAMM package repository☆32Mar 20, 2023Updated 2 years ago
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated 9 months ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆25Jul 17, 2025Updated 7 months ago
- Log file scanner used with EDA tools to classify errors and warnings☆12Nov 14, 2022Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- UVM interactive debug library☆35Updated this week
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Jan 27, 2026Updated last month
- SystemVerilog compiler and language services☆968Updated this week
- Assembly language (汇编语言程序设计 第三版 王爽)☆12Aug 17, 2022Updated 3 years ago
- MorphOS port of git☆12May 20, 2018Updated 7 years ago
- Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster☆11Oct 14, 2021Updated 4 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆252Feb 22, 2026Updated last week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆463Nov 4, 2025Updated 4 months ago
- UVM 1.2 port to Python☆259Feb 9, 2025Updated last year
- Source code for LEF/DEF☆11Oct 16, 2018Updated 7 years ago
- SPIR-V fragment shader GPU core based on RISC-V☆44May 26, 2021Updated 4 years ago
- A GUI to help users visualize the structure of a verilog HDL project☆12Jul 26, 2015Updated 10 years ago
- Simple class for driving a st7735s LCD display in python 3☆11Nov 1, 2018Updated 7 years ago