A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
☆131Aug 29, 2022Updated 4 years ago
Alternatives and similar repositories for AXI-SDCard-High-Speed-Controller
Users that are interested in AXI-SDCard-High-Speed-Controller are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆68Sep 23, 2022Updated 4 years ago
- AXI协议规范中文翻译版☆197Jul 5, 2022Updated 4 years ago
- An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器,可以从FAT16或FAT32格式的SD卡中读取文件。☆351Sep 14, 2023Updated 3 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆425Aug 10, 2026Updated 2 months ago
- Paging Debug tool for GDB using python☆13Jun 4, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- USB -> AXI Debug Bridge☆47Jun 5, 2021Updated 5 years ago
- 在RISC-V处理器上实现一个轻量级的Hypervisor。☆12Dec 25, 2020Updated 5 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 8 years ago
- ☆12Jul 20, 2022Updated 4 years ago
- ☆39Aug 12, 2015Updated 11 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆53Apr 23, 2020Updated 6 years ago
- AXI总线连接器☆111Mar 26, 2020Updated 6 years ago
- SDIO Device Verilog Core☆25Jul 25, 2018Updated 8 years ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆19Jan 25, 2022Updated 4 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- Hardware Architecture for 30fps Full-HD Guided Image Filter☆12Jul 20, 2019Updated 7 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆248Jul 16, 2023Updated 3 years ago
- AXI-Stream USB 2.0 HS Device Bridge (Verilog)☆17Apr 17, 2025Updated last year
- An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线),可以从FAT16或FA…☆99Sep 14, 2023Updated 3 years ago
- Verilog AXI components for FPGA implementation☆2,168Feb 27, 2025Updated last year
- SPI-Flash XIP Interface (Verilog)☆52Oct 24, 2021Updated 5 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A small RISC-V kernel coding by C, tested on sifive unmatched board.☆16Aug 20, 2022Updated 4 years ago
- User programs for rCore OS☆19Jun 7, 2022Updated 4 years ago
- What if everything is a io_uring?☆17Nov 10, 2022Updated 3 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆115May 8, 2026Updated 5 months ago
- MMC (and derivative standards) host controller☆26Sep 14, 2020Updated 6 years ago
- AHB3-Lite Interconnect☆110May 10, 2024Updated 2 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆13Jul 14, 2024Updated 2 years ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆126Oct 31, 2024Updated 2 years ago
- 国产VU13P加速卡资料☆86Mar 17, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 5 years ago
- Minimal DVI / HDMI Framebuffer☆87Aug 9, 2020Updated 6 years ago
- Imitate SDcard using FPGAs. 使用FPGA模拟伪装SD卡。☆140Sep 14, 2023Updated 3 years ago
- User-mode trap-and-emulate hypervisor for RISC-V☆14Feb 11, 2022Updated 4 years ago
- FPGA-based SATA-DMA Host Controller☆36Nov 20, 2025Updated 11 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆54Mar 31, 2026Updated 7 months ago
- UART -> AXI Bridge☆78Jul 1, 2021Updated 5 years ago