lizhirui / AXI-SDCard-High-Speed-Controller
A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
☆118Updated 2 years ago
Alternatives and similar repositories for AXI-SDCard-High-Speed-Controller
Users that are interested in AXI-SDCard-High-Speed-Controller are comparing it to the libraries listed below
Sorting:
- ☆64Updated 2 years ago
- AXI协议规范中文翻译版☆149Updated 2 years ago
- SDRAM controller with AXI4 interface☆92Updated 5 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆135Updated 11 months ago
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。☆176Updated last year
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆69Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆148Updated this week
- AXI总线连接器☆97Updated 5 years ago
- upgrade to e203 (a risc-v core)☆43Updated 4 years ago
- Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…☆182Updated last year
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆203Updated last year
- AMBA bus generator including AXI, AHB, and APB☆100Updated 3 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆120Updated last year
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。☆98Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…☆202Updated last year
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器，可实现视频压缩。☆123Updated last year
- 国产VU13P加速卡资料☆72Updated last month
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆105Updated 2 years ago
- AXI DMA 32 / 64 bits☆113Updated 10 years ago
- 使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例☆99Updated 7 months ago
- Cortex M0 based SoC☆73Updated 3 years ago
- ☆36Updated 9 years ago
- FFT generator using Chisel☆59Updated 3 years ago
- ☆63Updated 4 years ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆212Updated 4 years ago
- ☆62Updated 9 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago