Alternatives and similar repositories for Digital-IDE

Users that are interested in Digital-IDE are comparing it to the libraries listed below

• Nitcloud / Digital-IDE
  在vscode上的数字设计开发插件
  ☆388Updated 2 years ago
• xiaop1 / Verilog-Practice
  HDLBits website practices & solutions
  ☆758Updated last year
• WangXuan95 / USTC-RVSoC
  An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
  ☆419Updated 2 years ago
• XuanTongYao / XT_RISC-V_Soc
  一个极其简易的RV32I指令集单核MCU，用户级与特权级支持，仅运行机器模式。
  ☆41Updated 3 weeks ago
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,864Updated 3 months ago
• sin-x / FPGA
  数字IC相关资料
  ☆1,298Updated 4 months ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,634Updated 3 months ago
• openFPGA666 / FpgaGuide
  分享FPGA开发知识、优秀文章、学习网站以及开源项目。本项目收集了github中许多FPGA开源项目。
  ☆672Updated 2 years ago
• WangXuan95 / Xilinx-FPGA-PCIe-XDMA-Tutorial
  Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
  ☆711Updated 2 years ago
• CutestPanda / Opensoc
  包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等
  ☆119Updated 3 weeks ago
• Azalea8 / riscv_cpu
  riscv指令集，单周期以及五级流水线CPU
  ☆92Updated 10 months ago
• xupsh / Digital-Design-Lab
  ☆225Updated 4 years ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆1,000Updated 2 months ago
• viduraakalanka / HDL-Bits-Solutions
  This is a repository containing solutions to the problem statements given in HDL Bits website.
  ☆365Updated 2 years ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆294Updated 2 months ago
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆232Updated last year
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆161Updated 9 months ago
• Xinyang-ZHANG / RISC_V_RV32I_5stage_pipeline
  5 stage pipeline, single cycle risc-V implementation
  ☆24Updated last year
• ISRC-CAS / riscv-isa-manual-cn
  ☆194Updated last month
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,841Updated 8 months ago
• OSCPU / ysyx-workbench
  ☆155Updated last week
• WangXuan95 / FPGA-UART
  This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…
  ☆266Updated 2 years ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,074Updated last year
• flytt-away / FPGA-Video-Capture
  2023集创赛紫光同创杯一等奖项目
  ☆135Updated last year
• RongyeL / EasyAXI
  ☆77Updated 2 months ago
• 1391074994 / Verilog-Hdl-Format
  Verilog Hdl Format
  ☆27Updated 4 months ago
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆274Updated 2 years ago
• WangXuan95 / BSV_Tutorial_cn
  一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
  ☆593Updated 2 years ago
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆61Updated last year
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆69Updated 2 years ago