All in one vscode plugin for HDL development
☆1,120Mar 5, 2026Updated 3 months ago
Alternatives and similar repositories for Digital-IDE
Users that are interested in Digital-IDE are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 在vscode上的数字设计开发插件☆394Jan 27, 2023Updated 3 years ago
- NJU Virtual Board☆317Mar 24, 2026Updated 2 months ago
- VSH(SHell for Visualizing vcd file)项目为数字波形文件命令行查看器。☆25Dec 8, 2025Updated 6 months ago
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆651Aug 13, 2024Updated last year
- nscscc2024,HPU河南理工大学参赛作品,两仪处理器☆11Aug 24, 2024Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Must-have verilog systemverilog modules☆1,973Mar 12, 2026Updated 3 months ago
- Build mini linux for your own RISC-V emulator!☆24Sep 11, 2024Updated last year
- The Ultra-Low Power RISC-V Core☆1,856Aug 6, 2025Updated 10 months ago
- Verilog AXI components for FPGA implementation☆2,071Feb 27, 2025Updated last year
- 帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目☆5,491May 15, 2022Updated 4 years ago
- ☆21May 26, 2025Updated last year
- The official website of One Student One Chip project.☆12Feb 5, 2026Updated 4 months ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆56Jun 11, 2023Updated 3 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,593Jun 9, 2026Updated last week
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- An open-source EDA infrastructure and tools from netlist to GDS☆515Mar 11, 2026Updated 3 months ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- Open-source high-performance RISC-V processor☆7,068Updated this week
- "aura" my super-scalar O3 cpu core☆26May 25, 2024Updated 2 years ago
- Scala based HDL☆2,000Updated this week
- 体系结构研讨 + ysyx高阶大纲 (WIP☆215Oct 14, 2024Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆70Jan 8, 2024Updated 2 years ago
- A fork of Xiangshan for AI☆52Jun 5, 2026Updated last week
- ☆73May 11, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆807Updated this week
- Vivado诸多IP,包括图像处理等☆235Jul 28, 2024Updated last year
- A Convolutional Neural Network Accelerator implementation on FPGA, xilinx (xczu7ev-ffvc1156-2-i), The inference of yolov8 took 60ms.☆557Jul 17, 2025Updated 10 months ago
- A template project for beginning new Chisel work☆702Feb 24, 2026Updated 3 months ago
- ☆30Jun 19, 2025Updated 11 months ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Jun 7, 2026Updated last week
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆715Dec 14, 2025Updated 6 months ago
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆34Aug 9, 2024Updated last year
- A very simple and easy to understand RISC-V core.☆1,483Nov 9, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- 数字IC相关资料☆1,476Jul 1, 2025Updated 11 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,858Updated this week
- cocotb: Python-based chip (RTL) verification☆2,407Updated this week
- Scale-able EDA for FPGA, Verilog/Vivado/Quartus and more☆43Jul 28, 2024Updated last year
- automatic-verilog based on vimscript☆289Oct 24, 2023Updated 2 years ago
- 一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。☆609Sep 15, 2023Updated 2 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆614Aug 9, 2024Updated last year