Alternatives and similar repositories for Digital-IDE:

Users that are interested in Digital-IDE are comparing it to the libraries listed below

• Nitcloud / Digital-IDE
  在vscode上的数字设计开发插件
  ☆361Updated 2 years ago
• OSCPU / ysyx-workbench
  ☆141Updated 7 months ago
• openFPGA666 / FpgaGuide
  分享FPGA开发知识、优秀文章、学习网站以及开源项目。本项目收集了github中许多FPGA开源项目。
  ☆524Updated last year
• xupsh / Digital-Design-Lab
  ☆216Updated 4 years ago
• xiaop1 / Verilog-Practice
  HDLBits website practices & solutions
  ☆727Updated last year
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆267Updated 3 months ago
• WangXuan95 / USTC-RVSoC
  An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
  ☆395Updated last year
• viduraakalanka / HDL-Bits-Solutions
  This is a repository containing solutions to the problem statements given in HDL Bits website.
  ☆347Updated last year
• WangXuan95 / Xilinx-FPGA-PCIe-XDMA-Tutorial
  Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
  ☆561Updated last year
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆200Updated 8 months ago
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,750Updated 4 months ago
• CutestPanda / Opensoc
  包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等
  ☆70Updated this week
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆257Updated last year
• liangkangnan / tinyriscv
  A very simple and easy to understand RISC-V core.
  ☆1,194Updated last year
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,659Updated last month
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆153Updated 2 months ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆142Updated last month
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆60Updated 2 years ago
• xupsh / pp4fpgas-cn
  中文版 Parallel Programming for FPGAs
  ☆719Updated 7 months ago
• shinezyy / micro-arch-training
  How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design
  ☆539Updated 7 months ago
• 1391074994 / Verilog-Hdl-Format
  Verilog Hdl Format
  ☆20Updated 9 months ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆148Updated 5 months ago
• verimake-team / SparkRoad-V
  ☆62Updated 2 months ago
• doonny / basic_knowledge
  Things to learn for new students in the Lab for AI chips and systems of BJTU .
  ☆203Updated 4 months ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆417Updated 5 years ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆103Updated 2 years ago
• omarelhedaby / CNN-FPGA
  Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
  ☆477Updated 4 years ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,451Updated 5 months ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆99Updated 9 months ago
• Azalea8 / riscv_cpu
  riscv指令集，单周期以及五级流水线CPU
  ☆49Updated 2 months ago