Digital-EDA / Digital-IDE
All in one vscode plugin for HDL development
☆752Updated 2 months ago
Alternatives and similar repositories for Digital-IDE
Users that are interested in Digital-IDE are comparing it to the libraries listed below
Sorting:
- 在vscode上的数字设计开发插件☆373Updated 2 years ago
- Must-have verilog systemverilog modules☆1,768Updated last month
- ☆218Updated 4 years ago
- HDLBits website practices & solutions☆734Updated last year
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆93Updated this week
- NJU Virtual Board☆277Updated 3 weeks ago
- 分享FPGA开发知识、优秀文章、学习网站以及开源项目。本项目收集了github中许多FPGA开源项目。☆558Updated 2 years ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆593Updated last year
- The Ultra-Low Power RISC-V Core☆1,490Updated 7 months ago
- Vivado诸多IP,包括图像处理等☆208Updated 9 months ago
- An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。☆401Updated last year
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆348Updated last year
- ☆148Updated 3 weeks ago
- Verilog AXI components for FPGA implementation☆1,713Updated 2 months ago
- automatic-verilog based on vimscript☆262Updated last year
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆202Updated last year
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,035Updated 8 months ago
- An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器,可以从FAT16或FAT32格式的SD卡中读取文件。☆294Updated last year
- 一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。☆568Updated last year
- ☆144Updated 2 weeks ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆677Updated 6 months ago
- 我设计了一些数字集成电路的教学实验,供大家学习~☆26Updated 3 months ago
- 5 stage pipeline, single cycle risc-V implementation☆22Updated last year
- riscv指令集,单周期以及五级流水线CPU☆59Updated 4 months ago
- AMBA bus lecture material☆434Updated 5 years ago
- AXI协议规范中文翻译版☆149Updated 2 years ago
- CPU Design Based on RISCV ISA☆107Updated 11 months ago
- 数字IC相关资料☆1,138Updated 4 years ago
- An exquisite superscalar RV32GC processor.☆156Updated 4 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,272Updated last week