LeiWang1999 / Pynq-AcceleratorView external linksLinks
A easy general acc.
☆18Mar 22, 2021Updated 4 years ago
Alternatives and similar repositories for Pynq-Accelerator
Users that are interested in Pynq-Accelerator are comparing it to the libraries listed below
Sorting:
- Implement of vehicle flow statistics based on tensorflow and yolo3 with pyqt5 GUI.☆19Mar 24, 2023Updated 2 years ago
- Pointer analysis prototype (currently including anderson, steensgard).☆16Dec 20, 2021Updated 4 years ago
- A NVDLA Loadable Parser.☆12Mar 2, 2022Updated 3 years ago
- some sample caffemodel, prototxt, test images and pre compiled loadabes .☆13Apr 30, 2021Updated 4 years ago
- ☆18Apr 8, 2022Updated 3 years ago
- ☆100Mar 18, 2020Updated 5 years ago
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆22Oct 31, 2024Updated last year
- EQueue Dialect☆42Feb 3, 2022Updated 4 years ago
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆18May 12, 2022Updated 3 years ago
- PyTorch compilation tutorial covering TorchScript, torch.fx, and Slapo☆17Mar 13, 2023Updated 2 years ago
- A Python-like programming language for testing and experimenting with concurrent programs.☆32Oct 3, 2025Updated 4 months ago
- 集成电路设计大赛ARM杯作品,获得2021年ARM企业杯☆16Sep 26, 2021Updated 4 years ago
- ☆23Oct 7, 2021Updated 4 years ago
- A enumerator for MLIR, relying on the information given by IRDL.☆23Updated this week
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆25Nov 29, 2024Updated last year
- DAC System Design Contest 2020☆29Jun 11, 2020Updated 5 years ago
- njtech digital design. a fpga digital alarm system with Nexys A7 100T☆54Jun 11, 2019Updated 6 years ago
- ☆35Dec 12, 2021Updated 4 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆36Jan 16, 2025Updated last year
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆383Dec 27, 2023Updated 2 years ago
- A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…☆73May 30, 2025Updated 8 months ago
- TVMFuzz: fuzzing tensor-level intermediate representation in TVM☆30May 24, 2020Updated 5 years ago
- A real time Histogram of Oriented Gradients Implementation on FPGA☆32Jul 21, 2018Updated 7 years ago
- Artifact for OSDI'21 GNNAdvisor: An Adaptive and Efficient Runtime System for GNN Acceleration on GPUs.☆70Mar 2, 2023Updated 2 years ago
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆33Apr 11, 2024Updated last year
- ☆31Jun 15, 2022Updated 3 years ago
- PET: Optimizing Tensor Programs with Partially Equivalent Transformations and Automated Corrections☆125Jun 23, 2022Updated 3 years ago
- ☆77May 4, 2021Updated 4 years ago
- ☆11Jan 21, 2021Updated 5 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40May 17, 2022Updated 3 years ago
- Port of the LLVM compiler infrastructure to the time-predictable processor Patmos☆15Apr 2, 2025Updated 10 months ago
- ☆70Jun 16, 2021Updated 4 years ago
- ☆35Jul 24, 2019Updated 6 years ago
- MICRO 2023 Evaluation Artifact for TeAAL☆10Oct 26, 2023Updated 2 years ago
- ☆11Aug 23, 2023Updated 2 years ago
- ☆145Jan 30, 2025Updated last year
- RISC-V 64 CPU☆10Oct 4, 2025Updated 4 months ago
- [FCCM 2023] PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs☆13Jun 26, 2025Updated 7 months ago
- ☆12Feb 15, 2024Updated 2 years ago