LeiWang1999 / Pynq-Accelerator
A easy general acc.
☆16Updated 4 years ago
Alternatives and similar repositories for Pynq-Accelerator:
Users that are interested in Pynq-Accelerator are comparing it to the libraries listed below
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆56Updated 3 years ago
- ☆23Updated 3 years ago
- Public repostory for the DAC 2021 paper "Scaling up HBM Efficiency of Top-K SpMV forApproximate Embedding Similarity on FPGAs"☆14Updated 3 years ago
- EDA toolchain for processing-in-memory architectures, including an architecture synthesizer, a compiler, and a simulator☆11Updated 4 months ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆88Updated 6 months ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆41Updated 4 months ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆22Updated 11 months ago
- ☆34Updated last week
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆23Updated 2 years ago
- Ultra96 PYNQ入门之一次简单的总结☆14Updated 4 years ago
- Vivado HLS study notes, courses, documents.☆12Updated 5 years ago
- A DAG processor and compiler for a tree-based spatial datapath.☆13Updated 2 years ago
- An HBM FPGA based SpMV Accelerator☆12Updated 7 months ago
- ☆29Updated this week
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 2 years ago
- ☆12Updated last year
- ☆21Updated 2 years ago
- C++ RTL simulator for EIE(https://arxiv.org/abs/1602.01528)☆22Updated 4 years ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆83Updated 7 months ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- agile hardware-software co-design☆47Updated 3 years ago
- ☆20Updated 3 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- ☆70Updated 5 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- DAC System Design Contest 2020☆29Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆78Updated 8 months ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆19Updated 11 months ago