Nic30 / pyDigitalWaveTools
Python library for operations with VCD and other digital wave files
☆49Updated 10 months ago
Alternatives and similar repositories for pyDigitalWaveTools:
Users that are interested in pyDigitalWaveTools are comparing it to the libraries listed below
- Python bindings for slang, a library for compiling SystemVerilog☆57Updated 3 months ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆22Updated 3 years ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆60Updated last week
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆24Updated 2 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 7 months ago
- Making cocotb testbenches that bit easier☆29Updated 3 weeks ago
- Python interface for cross-calling with HDL☆32Updated last month
- ☆31Updated 3 months ago
- A flexible and scalable development platform for modern FPGA projects.☆23Updated 2 weeks ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- Python wrapper for verilator model☆82Updated last year
- hardware library for hwt (= ipcore repo)☆37Updated 5 months ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆33Updated 5 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆50Updated 7 months ago
- ☆20Updated this week
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 3 years ago
- SystemVerilog Linter based on pyslang☆30Updated 3 months ago
- Python Tool for UVM Testbench Generation☆52Updated 11 months ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆54Updated 2 months ago
- ☆26Updated last year
- Determines the modules declared and instantiated in a SystemVerilog file☆44Updated 7 months ago
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated last year
- ☆31Updated last year
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆23Updated 4 years ago
- Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.☆37Updated 9 months ago
- Mirror of Synopsys's Liberty parser library☆20Updated 6 years ago
- An automatic clock gating utility☆47Updated last week
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 10 months ago