Python library for operations with VCD and other digital wave files
☆55Nov 12, 2025Updated 3 months ago
Alternatives and similar repositories for pyDigitalWaveTools
Users that are interested in pyDigitalWaveTools are comparing it to the libraries listed below
Sorting:
- A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.☆11Jan 21, 2018Updated 8 years ago
- 🔍 Zoomable Waveform viewer for the Web☆43Nov 3, 2020Updated 5 years ago
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 3 years ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆31Updated this week
- 🕒 Static Timing Analysis diagram renderer☆13Dec 13, 2023Updated 2 years ago
- D3.js based wave (signal) visualizer☆67Aug 19, 2025Updated 6 months ago
- A VHDL Core Library.☆18Mar 29, 2017Updated 8 years ago
- Value Change Dump (VCD) parser☆38Jan 9, 2026Updated last month
- Python interface for cross-calling with HDL☆47Jan 23, 2026Updated last month
- D3.js and ELK based schematic visualizer☆115Feb 27, 2024Updated 2 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆33Dec 25, 2025Updated 2 months ago
- GHDL C extensions☆11Feb 20, 2020Updated 6 years ago
- Sphinx extension for visual documentation of hardware written in HWT☆11Nov 12, 2025Updated 3 months ago
- Python package for writing Value Change Dump (VCD) files.☆131Nov 10, 2024Updated last year
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆221Dec 23, 2025Updated 2 months ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- Streaming based VHDL parser.☆84Jul 15, 2024Updated last year
- Verilog hardware abstraction library☆46Updated this week
- Web-based HDL diagramming tool☆83May 1, 2023Updated 2 years ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆26Apr 29, 2021Updated 4 years ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 5 years ago
- Doppler effect on WaveForms☆17Sep 1, 2025Updated 5 months ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆317Jun 30, 2025Updated 7 months ago
- Python packages providing a library for Verification Stimulus and Coverage☆140Feb 18, 2026Updated last week
- Example of how to use UVM with Verilator☆37Feb 19, 2026Updated last week
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆103Mar 6, 2022Updated 3 years ago
- hardware library for hwt (= ipcore repo)☆44Dec 23, 2025Updated 2 months ago
- Fabric generator and CAD tools graphical frontend☆17Aug 5, 2025Updated 6 months ago
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 3 years ago
- An abstraction library for interfacing EDA tools☆755Feb 18, 2026Updated last week
- Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.☆67Oct 19, 2025Updated 4 months ago
- CoreIR Symbolic Analyzer☆74Oct 27, 2020Updated 5 years ago
- Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb☆50Feb 19, 2026Updated last week
- VexRiscv reference platforms for the pqriscv project☆16Mar 9, 2024Updated last year
- FuseSoc Verification Automation☆22Jul 21, 2022Updated 3 years ago
- SVA examples and demonstration☆18Sep 8, 2020Updated 5 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- Import and export IP-XACT XML register models☆37Nov 5, 2025Updated 3 months ago
- WaveDrom compatible python command line☆113Jun 2, 2023Updated 2 years ago