Python library for operations with VCD and other digital wave files
☆55May 19, 2026Updated 2 weeks ago
Alternatives and similar repositories for pyDigitalWaveTools
Users that are interested in pyDigitalWaveTools are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 3 years ago
- A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.☆11Jan 21, 2018Updated 8 years ago
- 🔍 Zoomable Waveform viewer for the Web☆43Nov 3, 2020Updated 5 years ago
- D3.js based wave (signal) visualizer☆68May 13, 2026Updated 3 weeks ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆34Mar 7, 2026Updated 3 months ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Value Change Dump (VCD) parser☆38Jan 9, 2026Updated 5 months ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆27Apr 29, 2021Updated 5 years ago
- A VHDL Core Library.☆18Mar 29, 2017Updated 9 years ago
- D3.js and ELK based schematic visualizer☆119May 13, 2026Updated 3 weeks ago
- 🕒 Static Timing Analysis diagram renderer☆13Dec 13, 2023Updated 2 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆225May 19, 2026Updated 2 weeks ago
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 6 months ago
- Verilog hardware abstraction library☆53May 24, 2026Updated 2 weeks ago
- Python interface for cross-calling with HDL☆51Mar 14, 2026Updated 2 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- Doppler effect on WaveForms☆17Sep 1, 2025Updated 9 months ago
- Streaming based VHDL parser.☆86Jul 15, 2024Updated last year
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 5 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆36Apr 9, 2026Updated 2 months ago
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated 10 months ago
- Python package for writing Value Change Dump (VCD) files.☆135Nov 10, 2024Updated last year
- Web-based HDL diagramming tool☆83May 1, 2023Updated 3 years ago
- Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.☆69Oct 19, 2025Updated 7 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- WaveDrom compatible python command line☆115Jun 2, 2023Updated 3 years ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆328Jun 30, 2025Updated 11 months ago
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆103Mar 6, 2022Updated 4 years ago
- Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb☆58Apr 2, 2026Updated 2 months ago
- An abstraction library for interfacing EDA tools☆770Apr 24, 2026Updated last month
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- hardware library for hwt (= ipcore repo)☆44May 30, 2026Updated last week
- SVA examples and demonstration☆18Sep 8, 2020Updated 5 years ago
- Example of how to use UVM with Verilator☆46Apr 20, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- GHDL C extensions☆12Feb 20, 2020Updated 6 years ago
- A library and command-line tool for querying a Verilog netlist.☆30Jun 13, 2022Updated 3 years ago
- A simple function to add wavedrom diagrams into an ipython notebook.☆24Jan 14, 2022Updated 4 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Mar 17, 2021Updated 5 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆145May 14, 2026Updated 3 weeks ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆28Nov 3, 2020Updated 5 years ago
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Jan 4, 2024Updated 2 years ago