scutdig / PyChip-py-hcl
A Hardware Construct Language
☆41Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for PyChip-py-hcl
- ☆31Updated last month
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆56Updated 10 months ago
- ☆56Updated 4 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆36Updated last year
- Basic floating-point components for RISC-V processors☆64Updated 4 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆14Updated last month
- chipyard in mill :P☆76Updated last year
- ☆31Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆71Updated 9 years ago
- ☆75Updated 2 years ago
- A hardware synthesis framework with multi-level paradigm☆37Updated last year
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆49Updated 4 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆43Updated 7 months ago
- Pick your favorite language to verify your chip.☆31Updated this week
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆35Updated 2 years ago
- ☆35Updated 6 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 4 months ago
- Pure digital components of a UCIe controller☆48Updated 3 weeks ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆57Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated 5 months ago
- Open source high performance IEEE-754 floating unit☆60Updated 8 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆20Updated 5 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- HLS for Networks-on-Chip☆31Updated 3 years ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆26Updated 4 years ago
- ☆64Updated 2 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆47Updated last year