scutdig / PyChip-py-hclLinks
A Hardware Construct Language
☆43Updated 3 years ago
Alternatives and similar repositories for PyChip-py-hcl
Users that are interested in PyChip-py-hcl are comparing it to the libraries listed below
Sorting:
- ☆33Updated 5 months ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- ☆81Updated last year
- chipyard in mill :P☆78Updated last year
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量 乘法累加加速器☆53Updated 5 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆19Updated 3 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆65Updated last year
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆35Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆65Updated 7 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated last year
- For contributions of Chisel IP to the chisel community.☆65Updated 9 months ago
- ☆73Updated this week
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 5 years ago
- Project repo for the POSH on-chip network generator☆50Updated 5 months ago
- ☆66Updated 3 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆24Updated 6 years ago
- Next generation CGRA generator☆113Updated this week
- ☆67Updated 2 years ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆57Updated last year
- Provides dot visualizations of chisel/firrtl circuits☆121Updated 2 years ago
- Chisel implementation of AES☆23Updated 5 years ago
- Chisel Learning Journey☆109Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆46Updated 3 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago