Alternatives and similar repositories for hdlConvertorAst:

Users that are interested in hdlConvertorAst are comparing it to the libraries listed below

• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆43Updated 4 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆35Updated 2 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆56Updated 3 years ago
• aolofsson / POSH
  ☆40Updated 5 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆55Updated last month
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆67Updated 6 months ago
• cclienti / svmodule
  SystemVerilog & Verilog Module I/O parser and printer
  ☆25Updated 3 years ago
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆36Updated 8 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆55Updated 4 years ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆55Updated last week
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆50Updated 8 months ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆46Updated this week
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆48Updated 3 weeks ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆62Updated 4 years ago
• chipsalliance / uvm-verilator
  ☆82Updated last year
• verilator / verilator-announce
  Announcements related to Verilator
  ☆38Updated 4 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 3 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 8 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆75Updated 10 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 4 months ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆25Updated 4 months ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 8 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆69Updated last week
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆60Updated 3 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆20Updated 5 years ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆33Updated 3 months ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆33Updated 3 years ago