Alternatives and similar repositories for VSRTL

Users that are interested in VSRTL are comparing it to the libraries listed below

• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆66Updated 5 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆88Updated last year
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆150Updated 2 weeks ago
• pieter3d / simview
  ☆87Updated last month
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆126Updated last year
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆103Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆89Updated last year
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆91Updated last month
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 5 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆103Updated 4 years ago
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• leros-dev / leros
  A Tiny Processor Core
  ☆114Updated 4 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆88Updated 3 weeks ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 4 months ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆68Updated last year
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆98Updated 3 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆86Updated 4 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆179Updated 6 months ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆101Updated 7 months ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆149Updated 6 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 8 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 8 months ago
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆168Updated last month
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆87Updated 5 years ago