☆142Feb 16, 2026Updated 3 months ago
Alternatives and similar repositories for vhd2vl
Users that are interested in vhd2vl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Jan 7, 2016Updated 10 years ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆325Jun 30, 2025Updated 10 months ago
- ☆19Aug 30, 2020Updated 5 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 3 months ago
- A JSON library implemented in VHDL.☆84Feb 8, 2026Updated 3 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- lightweight open HLS for FPGA rapid prototyping☆20Mar 22, 2018Updated 8 years ago
- IP-core package generator for AXI4/Avalon☆23Nov 25, 2018Updated 7 years ago
- Web-based HDL diagramming tool☆83May 1, 2023Updated 3 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 7 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Aug 7, 2023Updated 2 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Streaming based VHDL parser.☆86Jul 15, 2024Updated last year
- cocotb extension for nMigen☆17Feb 26, 2022Updated 4 years ago
- A tool for merging the MyHDL workflow with Vivado☆20May 13, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Simplified environment for litex☆14Oct 5, 2020Updated 5 years ago
- Open FPGA tools☆260Mar 30, 2020Updated 6 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆58Mar 13, 2025Updated last year
- UART cocotb module☆11Jun 30, 2021Updated 4 years ago
- ☆12Jun 4, 2021Updated 4 years ago
- SystemVerilog to Verilog conversion☆728Mar 28, 2026Updated last month
- A VHDL frontend for Yosys☆104Feb 27, 2017Updated 9 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Verification Utilities for MyHDL☆17Oct 26, 2023Updated 2 years ago
- FPGA ULX2/3 JTAG programmer☆43Nov 2, 2022Updated 3 years ago
- VHDL synthesis (based on ghdl)☆360May 14, 2026Updated last week
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Apr 19, 2026Updated last month
- public domain tools for FPGAs☆332Feb 7, 2017Updated 9 years ago
- Yosys Plugins☆22Jul 16, 2019Updated 6 years ago
- SVA examples and demonstration☆18Sep 8, 2020Updated 5 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆52Jun 5, 2022Updated 3 years ago
- ulx3s ghdl examples☆15Mar 6, 2021Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Building and deploying container images for open source electronic design automation (EDA)☆122Oct 3, 2024Updated last year
- VHDL library 4 FPGAs☆186Updated this week
- HDL tools layer for OpenEmbedded☆17Oct 20, 2024Updated last year
- ☆21Jul 28, 2016Updated 9 years ago
- Virtual development board for HDL design☆42Mar 31, 2023Updated 3 years ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- A header only C++11 library for functional coverage☆35Oct 5, 2022Updated 3 years ago