Translates IPXACT XML to synthesizable VHDL or SystemVerilog
☆64Oct 7, 2026Updated this week
Alternatives and similar repositories for ipxact2systemverilog
Users that are interested in ipxact2systemverilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Import and export IP-XACT XML register models☆40Nov 5, 2025Updated 11 months ago
- Python-based IP-XACT parser and utilities☆142Jun 13, 2024Updated 2 years ago
- ☆15May 10, 2019Updated 7 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆208Jun 3, 2026Updated 4 months ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 4 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆37Apr 15, 2020Updated 6 years ago
- 👾 Design ∪ Hardware☆79Sep 17, 2026Updated 3 weeks ago
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆263Sep 29, 2026Updated last week
- A Sphinx domain providing VHDL language support.☆21Jul 11, 2026Updated 2 months ago
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- An IP-XACT DOM for IEEE 1685-2014 in Python.☆31Updated this week
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆75Nov 22, 2019Updated 6 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Aug 24, 2026Updated last month
- Code snippets from articles published on www.amiq.com/consulting/blog☆37Jun 14, 2024Updated 2 years ago
- Reflection API for SystemVerilog☆14Mar 30, 2026Updated 6 months ago
- IPXACT Register Map Generator☆11May 9, 2021Updated 5 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 8 months ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆334Jun 30, 2025Updated last year
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆40Aug 31, 2026Updated last month
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 7 years ago
- Derived from https://sourceforge.net/projects/v2kparse☆45Sep 10, 2015Updated 11 years ago
- A VCD parser object☆41Jul 17, 2013Updated 13 years ago
- Useful UVM extensions☆28Jul 10, 2024Updated 2 years ago
- Systemverilog DPI-C call Python function☆29Mar 11, 2021Updated 5 years ago
- SystemRDL 2.0 language compiler front-end☆287Sep 22, 2026Updated 2 weeks ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆226Sep 20, 2026Updated 2 weeks ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆21Jul 4, 2026Updated 3 months ago
- 🇯 JSON encoder and decoder in pure SystemVerilog☆16Jul 7, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Python packages providing a library for Verification Stimulus and Coverage☆149Updated this week
- IP-core package generator for AXI4/Avalon☆22Nov 25, 2018Updated 7 years ago
- A header only C++11 library for functional coverage☆35Updated this week
- Sphinx Extension which generates various types of diagrams from Verilog code.☆65Sep 25, 2023Updated 3 years ago
- D3.js and ELK based schematic visualizer☆122May 13, 2026Updated 4 months ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆482Jun 10, 2026Updated 4 months ago
- ☆26Feb 15, 2025Updated last year