Translates IPXACT XML to synthesizable VHDL or SystemVerilog
☆65Jan 28, 2026Updated 3 months ago
Alternatives and similar repositories for ipxact2systemverilog
Users that are interested in ipxact2systemverilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆15May 10, 2019Updated 7 years ago
- Import and export IP-XACT XML register models☆37Nov 5, 2025Updated 6 months ago
- Python-based IP-XACT parser and utilities☆144Jun 13, 2024Updated last year
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 4 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆207Oct 21, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆36Apr 15, 2020Updated 6 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 3 months ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- Contains examples to start with Kactus2.☆23Aug 5, 2024Updated last year
- A Sphinx domain providing VHDL language support.☆21Dec 18, 2023Updated 2 years ago
- Useful UVM extensions☆27Jul 10, 2024Updated last year
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆254May 13, 2026Updated last week
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆21Nov 2, 2025Updated 6 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆26Feb 15, 2025Updated last year
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- IPXACT Register Map Generator☆11May 9, 2021Updated 5 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Nov 12, 2025Updated 6 months ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆325Jun 30, 2025Updated 10 months ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆74Nov 22, 2019Updated 6 years ago
- Code snippets from articles published on www.amiq.com/consulting/blog☆37Jun 14, 2024Updated last year
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆27Mar 1, 2021Updated 5 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆225May 13, 2026Updated last week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago
- Unified Verification Environment☆17Jan 17, 2017Updated 9 years ago
- A header only C++11 library for functional coverage☆35Oct 5, 2022Updated 3 years ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆65Sep 25, 2023Updated 2 years ago
- UVM Python Verification Agents Library☆15Mar 18, 2021Updated 5 years ago
- Cross EDA Abstraction and Automation☆41Nov 17, 2025Updated 6 months ago
- Code generation tool for control and status registers☆455Apr 19, 2026Updated last month
- Python packages providing a library for Verification Stimulus and Coverage☆145May 14, 2026Updated last week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- SystemRDL 2.0 language compiler front-end☆278Apr 10, 2026Updated last month
- IP-core package generator for AXI4/Avalon☆23Nov 25, 2018Updated 7 years ago
- ☆15Jun 27, 2024Updated last year
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 5 years ago
- A tool for modeling FSMs by VHDL or Verilog☆14May 15, 2026Updated last week
- Python interface for cross-calling with HDL☆50Mar 14, 2026Updated 2 months ago
- SystemVerilog VIP for AMBA APB protocol☆89Nov 11, 2021Updated 4 years ago