VHDL related news.
☆27Aug 12, 2026Updated this week
Alternatives and similar repositories for news
Users that are interested in news are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 4 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A VHDL Core Library.☆18Mar 29, 2017Updated 9 years ago
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆26Jun 23, 2026Updated last month
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago
- A Sphinx domain providing VHDL language support.☆21Jul 11, 2026Updated last month
- Example of Test Driven Design with VUnit☆16Nov 22, 2021Updated 4 years ago
- cryptography ip-cores in vhdl / verilog☆42Feb 20, 2021Updated 5 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆54Jun 5, 2022Updated 4 years ago
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆14Sep 22, 2025Updated 10 months ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆70Jul 29, 2026Updated 2 weeks ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Aug 3, 2026Updated last week
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 6 months ago
- A JSON library implemented in VHDL.☆85Jul 13, 2026Updated last month
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆85Feb 8, 2020Updated 6 years ago
- Virtual development board for HDL design☆42Mar 31, 2023Updated 3 years ago
- VHDL grammar for tree-sitter☆32Dec 20, 2023Updated 2 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆54Updated this week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆28Mar 17, 2026Updated 4 months ago
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.☆17Apr 10, 2025Updated last year
- CLI tool for RTL design space exploration on top of Vivado☆15Jun 5, 2023Updated 3 years ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆267Jul 30, 2026Updated 2 weeks ago
- Python scripts that help generating custom Sigasi Project and Libary configuration files☆18Feb 27, 2024Updated 2 years ago
- Streaming based VHDL parser.☆86Jul 15, 2024Updated 2 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆123Oct 3, 2024Updated last year
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆69Feb 16, 2026Updated 5 months ago
- Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.☆10Jul 22, 2020Updated 6 years ago
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- VHDL dependency analyzer☆25Mar 10, 2020Updated 6 years ago
- JavaScript action for users to easily install tip/nightly GHDL assets in GitHub Actions workflows☆16Jan 12, 2025Updated last year
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Mar 12, 2026Updated 5 months ago
- VUnit GitHub action☆19May 23, 2021Updated 5 years ago