andreaskuster / black-parrot-branch-predictorLinks
Branch Predictor Optimization for BlackParrot
☆15Updated last year
Alternatives and similar repositories for black-parrot-branch-predictor
Users that are interested in black-parrot-branch-predictor are comparing it to the libraries listed below
Sorting:
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆58Updated 3 weeks ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated 2 weeks ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆111Updated last week
- SystemC training aimed at TLM.☆31Updated 5 years ago
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- RISC-V Virtual Prototype☆172Updated 8 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Example code for Modern SystemC using Modern C++☆64Updated 2 years ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆183Updated this week
- Modeling Architectural Platform☆200Updated this week
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆51Updated 8 years ago
- Advanced Architecture Labs with CVA6☆65Updated last year
- CVA6 SDK containing RISC-V tools and Buildroot☆72Updated last month
- ☆182Updated last year
- RISC-V Virtual Prototype☆44Updated 3 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- A dynamic verification library for Chisel.☆154Updated 9 months ago
- Project repo for the POSH on-chip network generator☆49Updated 4 months ago
- Implementation of post-process coverage, and batch waveform search☆15Updated 3 years ago
- ☆97Updated last year
- ☆12Updated 3 months ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated last year
- HLS for Networks-on-Chip☆35Updated 4 years ago
- Public release☆57Updated 5 years ago
- ☆77Updated 10 years ago
- QEMU libsystemctlm-soc co-simulation demos.☆153Updated 2 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- RISC-V Core Local Interrupt Controller (CLINT)☆28Updated last month