andreaskuster / black-parrot-branch-predictorView external linksLinks
Branch Predictor Optimization for BlackParrot
☆15Mar 24, 2024Updated last year
Alternatives and similar repositories for black-parrot-branch-predictor
Users that are interested in black-parrot-branch-predictor are comparing it to the libraries listed below
Sorting:
- A RISC-V new instruction discovery tool [Work in Progress]☆15Dec 8, 2022Updated 3 years ago
- A Java Native Interface to libmdbx (https://gitflic.ru/project/erthink/libmdbx)☆26Nov 10, 2025Updated 3 months ago
- ☆27Feb 10, 2021Updated 5 years ago
- Development of a Network on Chip Simulation using SystemC.☆34Jul 14, 2017Updated 8 years ago
- Code for reproducing work of ICML 2019 paper: Memory-Optimal Direct Convolutions for Maximizing Classification Accuracy in Embedded Appli…☆12Jun 8, 2019Updated 6 years ago
- ☆41Apr 24, 2020Updated 5 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- The Complete Vue.JS Course for Beginners - Zero to Mastery, by Packt Publishing☆12Jul 20, 2023Updated 2 years ago
- BSc Project - Amirkabir University of Technology - Winter 2023☆11Jul 20, 2023Updated 2 years ago
- A simple 8086-CPU simulator using Verilog and Quartus II☆10Jul 9, 2018Updated 7 years ago
- This is a higan/Verilator co-simulation example/framework☆51Apr 17, 2018Updated 7 years ago
- RISCV lock-step checker based on Spike☆14Jan 23, 2026Updated 3 weeks ago
- Minimal startup code + Makefile for building bare-metal C programs for Cortex-M4☆11Jul 26, 2016Updated 9 years ago
- ☆10Nov 12, 2019Updated 6 years ago
- a simple header-only json serialization solution for c++ based on picojson☆13Dec 25, 2016Updated 9 years ago
- ☆12May 15, 2022Updated 3 years ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆11Jan 17, 2024Updated 2 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆17Nov 11, 2025Updated 3 months ago
- FPGA raycaster engine written in verilog☆12Apr 19, 2019Updated 6 years ago
- VGA LCD Core (OpenCores)☆15May 22, 2018Updated 7 years ago
- An implementation of 5-stages RISC-V CPU☆13Jul 22, 2022Updated 3 years ago
- Fast, compact floating point math for ARM Cortex-M0+ MCUs.☆11Apr 16, 2025Updated 10 months ago
- CIS 501: Computer Architecture Fall 2019☆22Apr 21, 2020Updated 5 years ago
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆16Updated this week
- Minimalistic RV32I RISC-V Processor in System Verilog☆19Sep 19, 2023Updated 2 years ago
- LinkIt Connect 7681 AT command support☆11Jan 27, 2016Updated 10 years ago
- ZC RISCV CORE☆12Dec 19, 2019Updated 6 years ago
- Fritzing parts for most common DIP ICs including 74LS Series and more, which is used in Digital Electronics or Logic Circuit and Design.☆19Jul 18, 2024Updated last year
- nextpnr portable FPGA place and route tool☆11Nov 30, 2020Updated 5 years ago
- A Beginner’s Guide to Assembly ARM language☆25Jun 18, 2024Updated last year
- Wishbone SATA Controller☆24Oct 16, 2025Updated 3 months ago
- Simulator for the MIC-1 CPU described in Andrew S. Tanenbaum’s textbook Structured Computer Organization☆12Jun 21, 2022Updated 3 years ago
- ☆15Dec 6, 2024Updated last year
- SPI Protocol Driver for TI CC1101 based RF communication modules.☆10Oct 30, 2015Updated 10 years ago
- Repo to hold HammerBlade PyTorch port. Based on PyTorch v1.4.0☆14Oct 4, 2022Updated 3 years ago
- Porting of (JavaScript version of) corewars8086 from codeguru xtreme to RISC-V cpu☆14Mar 25, 2019Updated 6 years ago
- An example of how to create a p2 composite update site during the build☆11Oct 18, 2019Updated 6 years ago
- Code for "Fast Sparse ConvNets" CVPR2020 submissions☆12Nov 20, 2019Updated 6 years ago
- A Python based 8085 assembler.☆13Feb 18, 2025Updated 11 months ago