Alternatives and similar repositories for RISCV-RV32I-Assembler

Users that are interested in RISCV-RV32I-Assembler are comparing it to the libraries listed below

• leros-dev / leros
  A Tiny Processor Core
  ☆110Updated last month
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆175Updated last month
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆86Updated last year
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆153Updated 3 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆112Updated last week
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆94Updated 2 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆179Updated last year
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆148Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆67Updated last year
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆165Updated this week
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆140Updated 5 years ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated last week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆158Updated 4 years ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆119Updated last week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 7 months ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆94Updated 9 months ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆115Updated 3 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated last month
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆141Updated 2 weeks ago
• merledu / nucleusrv
  NucleusRV - A 32-bit 5 staged pipelined risc-v core.
  ☆66Updated 2 months ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆124Updated 10 years ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆55Updated last year
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆103Updated 2 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 3 years ago
• riscv-admin / riscv-ovpsim
  ☆62Updated 4 years ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆101Updated last month