Alternatives and similar repositories for RISCV-RV32I-Assembler:

Users that are interested in RISCV-RV32I-Assembler are comparing it to the libraries listed below

• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆169Updated 7 months ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆85Updated 6 months ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆142Updated last year
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• chipsalliance / uvm-verilator
  ☆88Updated last year
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆150Updated 2 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆148Updated this week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆86Updated this week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆67Updated last year
• leros-dev / leros
  A Tiny Processor Core
  ☆107Updated this week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆111Updated 2 years ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆115Updated 9 years ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆107Updated this week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆181Updated last week
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆84Updated last month
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆154Updated 4 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆168Updated last year
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆129Updated this week
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆62Updated 6 months ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆102Updated 9 months ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆88Updated 11 months ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆115Updated 4 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆59Updated 4 months ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆74Updated 9 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆222Updated 3 months ago
• lowRISC / riscv-compliance
  TEMPORARY FORK of the riscv-compliance repository
  ☆22Updated 3 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆78Updated this week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆183Updated 8 months ago
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆14Updated 11 months ago