☆29Jan 18, 2021Updated 5 years ago
Alternatives and similar repositories for Chisel-Training
Users that are interested in Chisel-Training are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆35Apr 13, 2021Updated 5 years ago
- Experiments with fixed function renderers and ChiselHDL☆61Updated this week
- Lightweight Chisel template☆13May 30, 2020Updated 6 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- Contains source code for sin/cos table verification using UVM☆23Mar 9, 2021Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆49Nov 9, 2021Updated 4 years ago
- A MATLAB function library containing encoders, decoders and weight enumerators for Reed-Muller codes.☆13Aug 19, 2023Updated 2 years ago
- 🇯 JSON encoder and decoder in pure SystemVerilog☆16Jul 7, 2024Updated 2 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 5 years ago
- A Chisel implementation for an FPGA Pin Finder thru UART☆17Sep 24, 2024Updated last year
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆38Dec 24, 2024Updated last year
- Performance and diagnostic tools for Arm CMN on-chip interconnects☆31Aug 6, 2026Updated last week
- Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.☆13Nov 15, 2021Updated 4 years ago
- An implementation of a BinaryConnect network for cifar10☆11Nov 4, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Sources for the GNU Radio hugo website☆14Jul 4, 2026Updated last month
- ☆61Aug 30, 2021Updated 4 years ago
- Quadcopter control and pole balancing using deep reinforcement learning and hand gestures on ultra96☆10Oct 31, 2023Updated 2 years ago
- https://pypi.python.org/pypi/Verilog_VCD☆22Mar 16, 2017Updated 9 years ago
- ☆10Nov 12, 2019Updated 6 years ago
- ☆47Jul 31, 2026Updated 2 weeks ago
- ZC RISCV CORE☆12Dec 19, 2019Updated 6 years ago
- ☆19Dec 20, 2025Updated 7 months ago
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆18Dec 17, 2023Updated 2 years ago
- Main repo for Go2UVM source code, examples and apps☆21Mar 31, 2023Updated 3 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…☆27Jul 25, 2026Updated 2 weeks ago
- Branch Predictor Optimization for BlackParrot☆15Mar 24, 2024Updated 2 years ago
- Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"☆53May 16, 2026Updated 2 months ago
- RISC-V RV32IMAFC Core for MCU☆45May 20, 2026Updated 2 months ago
- openOCD including OpenRISC with adv_debug_sys☆16Jan 27, 2014Updated 12 years ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆81Oct 22, 2024Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- A cross platform, formally verified, open source, hyperRAM controller with simulator☆17Feb 22, 2019Updated 7 years ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆64Jan 28, 2026Updated 6 months ago
- This repository contains a set of examples of opencl code that can run on the zedboard zynq all programmable soc.☆16Jan 13, 2016Updated 10 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 3 years ago
- Coverview☆33Updated this week
- openairinterface.org: World’s Most Complete Open Source LTE Base Station (eNB) Software !☆20Sep 21, 2015Updated 10 years ago
- SystemVerilog & Verilog Module I/O parser and printer☆26Aug 5, 2026Updated last week