LCAI-TIHU / SW
LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V
☆23Updated 2 years ago
Alternatives and similar repositories for SW:
Users that are interested in SW are comparing it to the libraries listed below
- ☆44Updated 5 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆15Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- ☆29Updated 2 weeks ago
- ☆35Updated 4 years ago
- ☆33Updated 6 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated last month
- ☆30Updated 2 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Learn NVDLA by SOMNIA☆33Updated 5 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆9Updated 5 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆25Updated last week
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated 2 weeks ago
- cycle accurate Network-on-Chip Simulator☆27Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆16Updated 5 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated last week
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 6 months ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 3 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- ☆40Updated 4 months ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- A scalable Eyeriss model in SystemC.☆27Updated 2 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆34Updated 3 months ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- ☆71Updated 2 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Systolic-array based Deep Learning Accelerator generator☆24Updated 4 years ago