LCAI-TIHU / SW
LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V
☆23Updated 2 years ago
Alternatives and similar repositories for SW:
Users that are interested in SW are comparing it to the libraries listed below
- ☆44Updated 5 years ago
- ☆30Updated 2 years ago
- ☆33Updated 6 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 2 months ago
- ☆30Updated last month
- 关于深度学习算法、框架、编译器、加速器的一些理解☆15Updated 2 years ago
- A Toy-Purpose TPU Simulator☆18Updated 11 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆38Updated 2 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆34Updated 4 months ago
- ☆35Updated 4 years ago
- Ventus GPGPU ISA Simulator Based on Spike☆43Updated last month
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆26Updated 2 weeks ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆9Updated 5 years ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆14Updated 3 years ago
- ☆22Updated 2 years ago
- Learn NVDLA by SOMNIA☆33Updated 5 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆40Updated last year
- HLS implemented systolic array structure☆41Updated 7 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 3 years ago
- ☆16Updated 5 years ago
- A scalable Eyeriss model in SystemC.☆27Updated 2 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆57Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends☆34Updated last week
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated 3 weeks ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated 2 weeks ago
- FRAME: Fast Roofline Analytical Modeling and Estimation☆34Updated last year