Alternatives and similar repositories for SW

Users that are interested in SW are comparing it to the libraries listed below

• yonseicasl / NPUsim
  NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators
  ☆36Updated 5 months ago
• zeasa / nvdla-compiler
  ☆44Updated 5 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• sfu-arch / SpGEMM
  ☆35Updated 4 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 3 months ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• suchandler96 / gem5-NVDLA
  ☆31Updated 2 months ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆28Updated 3 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆54Updated this week
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆39Updated 2 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆53Updated 2 months ago
• pulp-platform / dram_rtl_sim
  ☆15Updated 9 months ago
• gem5-X / TiC-SAT
  ☆17Updated last month
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆28Updated this week
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• pulp-platform / ITA
  ☆47Updated 2 months ago
• lycfly / EasyNPU
  A small Neural Network Processor for Edge devices.
  ☆11Updated 2 years ago
• nietzhuang / Cycle-accurate-Eyeriss-model
  A scalable Eyeriss model in SystemC.
  ☆28Updated 2 years ago
• zhehaoxu / ai-talk
  关于深度学习算法、框架、编译器、加速器的一些理解
  ☆15Updated 2 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆79Updated 3 years ago
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆29Updated last month
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆25Updated 4 years ago
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆16Updated 11 months ago
• openasic-org / xkDLA
  xkDLA：XinKai Deep Learning Accelerator (RTL)
  ☆34Updated last year
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• SameLight / ITRI-OpenDLA
  Express DLA implementation for FPGA, revised based on NVDLA.
  ☆9Updated 5 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆57Updated 3 years ago