Verilog Ethernet Switch (layer 2)
☆60Oct 18, 2023Updated 3 years ago
Alternatives and similar repositories for eth_switch
Users that are interested in eth_switch are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 100 MB/s Ethernet MAC Layer Switch☆15Jul 17, 2014Updated 12 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆59Oct 9, 2023Updated 3 years ago
- 10Gb Ethernet Switch☆279Sep 17, 2026Updated last month
- AXI-Stream USB 2.0 HS Device Bridge (Verilog)☆16Apr 17, 2025Updated last year
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 10 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆10Jul 29, 2018Updated 8 years ago
- Project in course “FPGA Design for Communication Systems”☆16Dec 30, 2023Updated 2 years ago
- Wishbone SATA Controller☆28Sep 17, 2026Updated last month
- NetFPGA 1G CML Live development repository☆14Jun 23, 2020Updated 6 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆37May 12, 2020Updated 6 years ago
- Ethernet switch implementation written in Verilog☆66Jun 13, 2023Updated 3 years ago
- ☆42Jun 9, 2022Updated 4 years ago
- OpenTSN3.4开源项目的新特性：（1）交换平面深度解耦，硬件代码由TSS（时间敏感交换），HCP（硬件控制点）和OSMAC（Opensync MAC）实现。（2）集成了Opensync开源实现，支持802.1AS和AS6802两种时间同步协议；（3）集成了TSN硬件仿…☆43Aug 13, 2022Updated 4 years ago
- TCP Offload Engine☆79Nov 18, 2017Updated 8 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆15Aug 1, 2023Updated 3 years ago
- 实现带有BD（Buffer Description缓存描述符）的四通道DMA控制器设计，每个通道包括配置寄存器模块，源端控制模 块，缓存模块和目的端控制模块☆12Sep 12, 2023Updated 3 years ago
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆47Nov 24, 2014Updated 11 years ago
- LPC (Low Pin Count) interface peripheral module in pure Verilog☆16Jan 15, 2024Updated 2 years ago
- ☆12May 13, 2025Updated last year
- AMD OpenNIC Shell includes the HDL source files☆160Jan 2, 2025Updated last year
- TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.☆78Sep 30, 2026Updated last month
- USB -> AXI Debug Bridge☆47Jun 5, 2021Updated 5 years ago
- A Hardware MD5 Cracker for the Cyclone V SoC☆12Mar 25, 2015Updated 11 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆90Jun 27, 2022Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆46Jan 6, 2023Updated 3 years ago
- Verilog Ethernet components for FPGA implementation☆3,143Feb 27, 2025Updated last year
- Ethernet MAC 10/100 Mbps☆39Oct 31, 2021Updated 4 years ago
- ☆92May 4, 2017Updated 9 years ago
- ☆15Jul 28, 2022Updated 4 years ago
- RTL code of some arbitration algorithm☆16Oct 10, 2026Updated 2 weeks ago
- round robin arbiter☆78Jul 17, 2014Updated 12 years ago
- Example designs for FPGA Drive FMC☆305Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- SPI-Flash XIP Interface (Verilog)☆52Oct 24, 2021Updated 5 years ago
- PTPv2 hardware engine design for 10G Ethernet, described in Verilog HDL☆19May 27, 2025Updated last year
- ☆22Nov 7, 2019Updated 6 years ago
- FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC☆60Feb 3, 2023Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆74Sep 17, 2026Updated last month
- UART -> AXI Bridge☆78Jul 1, 2021Updated 5 years ago