Verilog Ethernet Switch (layer 2)
☆59Oct 18, 2023Updated 2 years ago
Alternatives and similar repositories for eth_switch
Users that are interested in eth_switch are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 100 MB/s Ethernet MAC Layer Switch☆15Jul 17, 2014Updated 12 years ago
- 10Gb Ethernet Switch☆274Updated this week
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 9 years ago
- ☆10Jul 29, 2018Updated 8 years ago
- Project in course “FPGA Design for Communication Systems”☆16Dec 30, 2023Updated 2 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- TCAM (Ternary Content-Addressable Memory) in Verilog☆59Oct 9, 2023Updated 2 years ago
- Wishbone SATA Controller☆28Aug 24, 2026Updated last week
- ☆15Aug 1, 2023Updated 3 years ago
- ☆42Jun 9, 2022Updated 4 years ago
- TCP Offload Engine☆79Nov 18, 2017Updated 8 years ago
- A Hardware MD5 Cracker for the Cyclone V SoC☆12Mar 25, 2015Updated 11 years ago
- AMD OpenNIC Shell includes the HDL source files☆153Jan 2, 2025Updated last year
- LPC (Low Pin Count) interface peripheral module in pure Verilog☆17Jan 15, 2024Updated 2 years ago
- ☆15Jul 28, 2022Updated 4 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Ethernet switch implementation written in Verilog☆66Jun 13, 2023Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆52Oct 24, 2021Updated 4 years ago
- RTL code of some arbitration algorithm☆17Aug 25, 2019Updated 7 years ago
- OpenTSN3.4开源项目的新特性:(1)交换平面深度解耦,硬件代码由TSS(时间敏感交换),HCP(硬件控制点)和OSMAC(Opensync MAC)实现。(2)集成了Opensync开源实现,支持802.1AS和AS6802两种时间同步协议;(3)集成了TSN硬件仿…☆43Aug 13, 2022Updated 4 years ago
- ☆89Jun 27, 2022Updated 4 years ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆13Aug 14, 2020Updated 6 years ago
- UART -> AXI Bridge☆78Jul 1, 2021Updated 5 years ago
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆32May 18, 2019Updated 7 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆46Jan 6, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆20Nov 7, 2019Updated 6 years ago
- PTPv2 hardware engine design for 10G Ethernet, described in Verilog HDL☆19May 27, 2025Updated last year
- Revision Control Labs and Materials☆26Jan 23, 2018Updated 8 years ago
- 基于arm cortex-m0内核的xillinx fpga sopc工程项目☆13May 28, 2019Updated 7 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.☆71Jun 7, 2026Updated 2 months ago
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆46Nov 24, 2014Updated 11 years ago
- Verilog Ethernet components for FPGA implementation☆3,077Feb 27, 2025Updated last year
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆37Mar 13, 2025Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Hardware implementation of HDR image producing algorithm☆16Sep 30, 2022Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆39Oct 31, 2021Updated 4 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆16Nov 8, 2025Updated 9 months ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆957Aug 3, 2026Updated 3 weeks ago
- An Ethernet MAC conforming to IEEE 802.3☆24May 13, 2017Updated 9 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago
- Gowin USB3.0 Device Controller IP☆17Aug 20, 2024Updated 2 years ago