Alternatives and similar repositories for Network-On-Chip

Users that are interested in Network-On-Chip are comparing it to the libraries listed below

• alice820621 / A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM
  A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…
  ☆15Updated 7 years ago
• imokanj / clk_rst_agent
  UVM Clock and Reset Agent
  ☆13Updated 8 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆35Updated last week
• briandong / regModel
  This script builds the UVM register model, based on pre-defined address map in markdown (mk) style
  ☆12Updated 7 years ago
• svunit / svmock
  A mock framework for use with SVUnit
  ☆19Updated 2 years ago
• avashist003 / FIFO_SystemVerilog_Assertion
  Synchronous FIFO design & verification using systemVerilog Assertions
  ☆17Updated 4 years ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆26Updated 5 years ago
• taichi-ishitani / tvip-common
  ☆14Updated last year
• muneebullashariff / uart_vip
  Verification IP for UART protocol
  ☆20Updated 5 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated 11 months ago
• ansonn / esl_systemc
  systemc建模相关
  ☆27Updated 11 years ago
• pulp-platform / axi_llc
  ☆32Updated 3 weeks ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆31Updated 5 years ago
• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆13Updated 10 years ago
• muneebullashariff / pulpino_soc_uvm_testbench
  UVM testbench for verifying the Pulpino SoC
  ☆14Updated 5 years ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆19Updated 7 years ago
• arm-university / SoC-design-and-prototyping-Research-Enablement-Kit
  SoC design & prototyping
  ☆16Updated 6 months ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• JoseIuri / UVM_Python
  This repository contains an example of the connection between an UVM Testbench and a Python reference model.
  ☆12Updated 6 years ago
• jiayi-wang98 / lpddr4_memory_controller
  ☆10Updated 3 years ago
• PacoReinaCampo / SoC-DV
  System on Chip verified with UVM/OSVVM/FV
  ☆32Updated last week
• open-dv / dma_axi
  ☆16Updated 6 years ago
• jg-fossh / uvm-python-verification-lib
  UVM Python Verification Agents Library
  ☆15Updated 4 years ago
• systemc / uvmc
  Connecting SystemC with SystemVerilog
  ☆41Updated 13 years ago
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆31Updated 7 years ago
• amiq-consulting / yamm
  YAMM package repository
  ☆32Updated 2 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆72Updated 6 years ago
• pulp-platform / axi_spi_master
  ☆22Updated 6 years ago
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆31Updated 4 years ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆35Updated 5 years ago