cepdnaclk / e17-4yp-Neuromorphic-NoC-Architecture-for-SNNsLinks
This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, and test it on FPGA.
☆21Updated last year
Alternatives and similar repositories for e17-4yp-Neuromorphic-NoC-Architecture-for-SNNs
Users that are interested in e17-4yp-Neuromorphic-NoC-Architecture-for-SNNs are comparing it to the libraries listed below
Sorting:
- SNN on FPGA☆10Updated 3 years ago
- ☆19Updated 4 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆34Updated 5 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆23Updated 5 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆59Updated 5 months ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆12Updated 2 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 6 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆24Updated 7 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆13Updated last year
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆61Updated 2 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆19Updated 9 months ago
- Spiking Neural Network RTL Implementation☆58Updated 4 years ago
- A repository FPGA-friendly SNN models☆33Updated 4 years ago
- FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)☆11Updated last year
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆38Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆37Updated last year
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆59Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆34Updated 3 years ago
- FPGA Design of a Spiking Neural Network.☆41Updated last year
- ☆17Updated 4 years ago
- ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.☆187Updated 6 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- A nest brain simulator based on FPGA(LIF NEURON)☆14Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- Tensor Processing Unit implementation in Verilog☆8Updated 4 months ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆17Updated 5 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆12Updated 4 years ago
- ☆25Updated 3 years ago
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆15Updated 2 years ago