Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of the most complex operations. This SFU implements the Piecewise Polynomial Approximation, which provides high performance, low area costs and good accuracy for real implementation of hardware.
☆16Sep 21, 2025Updated 5 months ago
Alternatives and similar repositories for SFU-Piecewise-Polynomial-Approximation
Users that are interested in SFU-Piecewise-Polynomial-Approximation are comparing it to the libraries listed below
Sorting:
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆119May 11, 2023Updated 2 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- ☆11May 8, 2022Updated 3 years ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Oct 31, 2021Updated 4 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- Precision Time Protocol (IEEE 1588 v2) for PIC32MX MCUs (DP83640 PHY)☆11Jun 28, 2019Updated 6 years ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- With the rapid adoption of smartphones, tablets, and mobile apps, they are increasingly becoming part of children’s daily life for amusem…☆12Apr 7, 2017Updated 8 years ago
- Implemented a two-level (L1 and L2) cache simulator in C++ with round robin eviction policy☆10Jan 4, 2017Updated 9 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆13Oct 26, 2019Updated 6 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆15May 16, 2021Updated 4 years ago
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆16Feb 17, 2026Updated 2 weeks ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 4 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- Superscalar Out-of-Order NPU Design on FPGA☆11May 17, 2024Updated last year
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated last year
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 7 years ago
- ☆12Nov 11, 2015Updated 10 years ago
- This repository is used to store RTL code for combining a single video source from multiple video sources.☆18Oct 28, 2024Updated last year
- MATLAB functions that use the java driver for access to MongoDB databases☆13Oct 9, 2017Updated 8 years ago
- ☆13May 5, 2023Updated 2 years ago