Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of the most complex operations. This SFU implements the Piecewise Polynomial Approximation, which provides high performance, low area costs and good accuracy for real implementation of hardware.
☆19Sep 21, 2025Updated last year
Alternatives and similar repositories for SFU-Piecewise-Polynomial-Approximation
Users that are interested in SFU-Piecewise-Polynomial-Approximation are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 本项目是一个基于RISC-V指令集架构的向量处理器(Vector Processing Unit, VPU)设计,旨在实现RISC-V向量扩展(RVV)规范中定义的向量运算功能。涵盖了处理器设计、计算机体系结构和硬件描述语言编程等多个领域的知识。☆21May 8, 2025Updated last year
- A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…☆14Aug 23, 2024Updated 2 years ago
- A simulator for the memory controller scheduler of a 12-core, 4.8 GHz processor using a DDR5 DIMM. It supports multiple DRAM scheduling a…☆14Dec 6, 2023Updated 2 years ago
- Personal Project, Implementation of tinyNPU☆13Oct 14, 2024Updated 2 years ago
- A computing in memory project based on Python, which includes training, quantization, hardware implementation performance estimation.☆10Jul 17, 2024Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆25Apr 25, 2025Updated last year
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 7 years ago
- 将 Verilog 设计规范、流水线模式与 FPGA 优化笔记结构化为可查询的本地知识库,供本地智能代理或脚本检索并返回带出处的实现建议与示例代码。☆28May 23, 2026Updated 5 months ago
- A Preprocessor for Verilog HDL written in C++☆11May 26, 2012Updated 14 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 4 years ago
- ☆13Oct 11, 2023Updated 3 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆24Updated this week
- Motion Estimation implementation by using Verilog HDL☆14Jun 17, 2024Updated 2 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆13Aug 26, 2023Updated 3 years ago
- With the rapid adoption of smartphones, tablets, and mobile apps, they are increasingly becoming part of children’s daily life for amusem…☆12Apr 7, 2017Updated 9 years ago
- axi video dma ip in verilog☆11Aug 22, 2020Updated 6 years ago
- An analytical model and map-space exploration tool for GEMMs on HW Accelerators based on spatial architectures☆10Oct 17, 2025Updated last year
- A High-Level DRAM Timing, Power and Area Exploration Tool☆34Jul 29, 2020Updated 6 years ago
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆22Apr 12, 2026Updated 6 months ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆33Feb 6, 2023Updated 3 years ago
- SystemVerilog implementation of a Dynamically Weighted Round Robin arbiter☆14Mar 21, 2017Updated 9 years ago
- Tensorflow implementation of CARN☆10Oct 3, 2018Updated 8 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆41Dec 22, 2023Updated 2 years ago
- Direct Access Memory for MPSoC☆13Updated this week
- Matrix multiplication accelerator on ZYNQ SoC.☆13Apr 29, 2025Updated last year
- ☆22Oct 12, 2026Updated 3 weeks ago
- ☆11Jun 28, 2020Updated 6 years ago
- ☆11Oct 10, 2021Updated 5 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆125May 11, 2023Updated 3 years ago
- Benchmark and resources for single super-resolution algorithms☆10Apr 14, 2017Updated 9 years ago
- ☆18Sep 16, 2020Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- RTL Interview Questions☆12Mar 23, 2019Updated 7 years ago
- AI Chip project☆35Jul 14, 2021Updated 5 years ago
- a Computing In Memory emULATOR framework☆16May 19, 2024Updated 2 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Mar 15, 2018Updated 8 years ago
- FPU Generator☆21Updated this week
- ☆10Apr 4, 2025Updated last year
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago