KULeuven-MICAS / htvm
Efficient Neural Network Deployment on Heterogenous TinyML Platforms
☆14Updated last year
Alternatives and similar repositories for htvm:
Users that are interested in htvm are comparing it to the libraries listed below
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆34Updated last week
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆76Updated 2 months ago
- ☆90Updated 10 months ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆24Updated 7 months ago
- ☆59Updated last year
- ☆71Updated 2 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆29Updated 5 months ago
- ☆57Updated 4 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 5 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated 2 months ago
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 7 months ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆22Updated 3 years ago
- NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions☆29Updated 3 weeks ago
- ☆23Updated 2 years ago
- Algorithmic C Machine Learning Library☆23Updated 4 months ago
- ☆33Updated 6 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆43Updated 2 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- ☆10Updated 4 months ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆34Updated 2 weeks ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆39Updated 6 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆74Updated 3 years ago
- DNN Compiler for Heterogeneous SoCs☆36Updated last week
- CGRA framework with vectorization support.☆29Updated this week
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆50Updated last month
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆14Updated 6 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 6 months ago