KULeuven-MICAS / htvm
Efficient Neural Network Deployment on Heterogenous TinyML Platforms
☆14Updated last year
Alternatives and similar repositories for htvm:
Users that are interested in htvm are comparing it to the libraries listed below
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆30Updated this week
- DNN Compiler for Heterogeneous SoCs☆26Updated this week
- ☆10Updated 3 months ago
- ☆71Updated 2 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆32Updated last year
- A DAG processor and compiler for a tree-based spatial datapath.☆13Updated 2 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆48Updated last week
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Designs for finalist teams of the DAC System Design Contest☆36Updated 4 years ago
- DUTH RISC V Microprocessor for High Level Synthesis☆10Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆77Updated 7 months ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆28Updated 3 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated this week
- A fast, accurate trace-based simulator for High-Level Synthesis.☆44Updated 3 weeks ago
- Algorithmic C Machine Learning Library☆22Updated 2 months ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆22Updated 2 years ago
- ☆56Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆85Updated 5 months ago
- ☆25Updated 2 months ago
- ☆83Updated 8 months ago
- ☆56Updated 4 years ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆22Updated 3 years ago
- ACM TODAES Best Paper Award, 2022☆24Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆9Updated 3 years ago
- ☆33Updated this week
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆46Updated last year
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 5 months ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆55Updated 3 years ago