Alternatives and similar repositories for tinyvers

Users that are interested in tinyvers are comparing it to the libraries listed below

• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆62Updated last month
• hyoukjun / microswitch-noc
  ☆29Updated 6 years ago
• kuladeepsaireddy / OpenNoc
  ☆40Updated 6 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆37Updated 8 months ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆55Updated 4 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆76Updated 6 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆82Updated 2 months ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆39Updated 4 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆44Updated 3 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆25Updated 4 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆23Updated 4 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆82Updated 11 years ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆17Updated last year
• avikram2 / RISCVPipelinedProcessor
  Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…
  ☆14Updated 3 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆33Updated last year
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆80Updated 8 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆26Updated last year
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Updated 4 years ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆29Updated 4 years ago
• Youssefmdany / RISC-V-Single-Cycle-Processor-Integrated-With-a-Cache-Memory-System-From-RTL-To-GDS
  RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS
  ☆11Updated last year
• ljgibbslf / basic_cache_core
  ☆31Updated 5 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆28Updated 3 months ago
• tharunchitipolu / Dadda-Multiplier-using-CSA
  Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
  ☆40Updated last year
• freecores / an-fpga-implementation-of-low-latency-noc-based-mpsoc
  NoC based MPSoC
  ☆11Updated 11 years ago
• pulp-platform / hwpe-stream
  IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
  ☆21Updated 3 weeks ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆57Updated last month
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆70Updated 3 years ago
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆17Updated 7 years ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆14Updated 8 years ago