KULeuven-MICAS / tinyversLinks
TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.
☆19Updated 2 years ago
Alternatives and similar repositories for tinyvers
Users that are interested in tinyvers are comparing it to the libraries listed below
Sorting:
- ☆27Updated 5 years ago
- SoC Based on ARM Cortex-M3☆32Updated 3 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated 2 weeks ago
- ☆34Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆57Updated 10 months ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- HLS for Networks-on-Chip☆35Updated 4 years ago
- ☆29Updated 5 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆26Updated 2 years ago
- EE 272B - VLSI Design Project☆13Updated 4 years ago
- ☆15Updated 2 years ago
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆34Updated 10 months ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- SystemVerilog modules and classes commonly used for verification☆50Updated 7 months ago
- Design and UVM-TB of RISC -V Microprocessor☆25Updated last year
- ☆77Updated 10 years ago
- Template for project1 TPU☆19Updated 4 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 6 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- DUTH RISC-V Microprocessor☆20Updated 8 months ago