Aayush-Ankit / puma-simulatorLinks
[ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and runs ML models compiled using the puma compiler.
☆67Updated 2 years ago
Alternatives and similar repositories for puma-simulator
Users that are interested in puma-simulator are comparing it to the libraries listed below
Sorting:
- PUMA Compiler☆29Updated 5 years ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆47Updated last year
- ☆31Updated 4 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆139Updated 3 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- ☆43Updated 4 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆93Updated 5 months ago
- NVSim - A performance, energy and area estimation tool for non-volatile memory (NVM)☆122Updated 7 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆74Updated 6 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆70Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"☆41Updated last month
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆38Updated 2 years ago
- PIMeval simulator and PIMbench suite☆33Updated 2 months ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆37Updated 2 months ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆56Updated 4 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆64Updated 9 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆84Updated last year
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆65Updated 5 months ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆35Updated 3 years ago
- Neural Network Evaluation Tool on Crossbar-based Accelerator with Resistive Memory☆41Updated 5 years ago
- RTL implementation of Flex-DPE.☆112Updated 5 years ago
- ☆29Updated 3 years ago
- ☆92Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆72Updated last year
- ☆40Updated last year