suarezvictor / CflexHDL

Related projects: ⓘ

• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆162Updated 3 weeks ago
• ZipCPU / vgasim
  A Video display simulator
  ☆154Updated last month
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆154Updated 6 months ago
• smunaut / doom_riscv
  Doom classic port to lightweight RISC‑V
  ☆80Updated 2 years ago
• olofk / corescore
  CoreScore
  ☆135Updated last week
• JulianKemmerer / PipelineC-Graphics
  Graphics demos
  ☆95Updated 5 months ago
• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆89Updated last month
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆107Updated 11 months ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆206Updated 7 months ago
• pieter3d / simview
  ☆76Updated 6 months ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆147Updated 5 months ago
• ZipCPU / eth10g
  10Gb Ethernet Switch
  ☆147Updated 6 months ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆78Updated 4 years ago
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆104Updated this week
• ToNi3141 / RasteriCEr
  Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)
  ☆32Updated 2 years ago
• tomverbeure / rt
  A Full Hardware Real-Time Ray-Tracer
  ☆89Updated last year
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆111Updated 2 years ago
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆105Updated last month
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆167Updated this week
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆34Updated last year
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆54Updated this week
• nullobject / sdram-fpga
  A FPGA core for a simple SDRAM controller.
  ☆113Updated 2 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆174Updated 2 weeks ago
• vmunoz82 / eda_tools
  A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, …
  ☆39Updated last year
• yne / vcd
  VCD file (Value Change Dump) command line viewer
  ☆106Updated last year
• ldoolitt / vhd2vl
  ☆117Updated last year
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆63Updated 2 years ago
• zxmarcos / huedeon-gpu
  FPGA GPU design for DE1-SoC
  ☆70Updated 2 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆70Updated 2 weeks ago
• chipsalliance / synlig
  SystemVerilog support for Yosys
  ☆156Updated this week