Alternatives and similar repositories for CflexHDL

Users that are interested in CflexHDL are comparing it to the libraries listed below

• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆180Updated last week
• JulianKemmerer / PipelineC-Graphics
  Graphics demos
  ☆110Updated last year
• smunaut / doom_riscv
  Doom classic port to lightweight RISC‑V
  ☆94Updated 3 years ago
• olofk / corescore
  CoreScore
  ☆162Updated last week
• ZipCPU / vgasim
  A Video display simulator
  ☆171Updated 3 months ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆175Updated last year
• openXC7 / toolchain-installer
  Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
  ☆87Updated 2 months ago
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆52Updated 3 months ago
• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆107Updated last year
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆221Updated last year
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆105Updated 2 weeks ago
• pieter3d / simview
  ☆79Updated last year
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 4 months ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆32Updated 2 years ago
• olofk / vidbo
  Virtual Development Board
  ☆60Updated 3 years ago
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆139Updated 4 months ago
• tomverbeure / rt
  A Full Hardware Real-Time Ray-Tracer
  ☆108Updated 2 years ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆181Updated this week
• ecilasun / tinysys
  A tiny system built on a small QMTECH board
  ☆108Updated 4 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆94Updated last week
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆46Updated 6 months ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆151Updated 3 months ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆244Updated 10 months ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆66Updated this week
• MichaelBell / tinyQV
  A Risc-V SoC for Tiny Tapeout
  ☆30Updated last week
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆159Updated 5 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year
• dan-rodrigues / icestation-32
  Compact FPGA game console
  ☆166Updated last year
• nullobject / sdram-fpga
  A FPGA core for a simple SDRAM controller.
  ☆120Updated 3 years ago
• zxmarcos / huedeon-gpu
  FPGA GPU design for DE1-SoC
  ☆74Updated 3 years ago