RV64IMAC modelling using System Verilog HDL
☆26Aug 10, 2024Updated last year
Alternatives and similar repositories for RV64IMAC
Users that are interested in RV64IMAC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Source-Opened RISCV for Crypto☆18Jan 18, 2022Updated 4 years ago
- Open source tools for IC design☆14Dec 12, 2024Updated last year
- ☆16Jul 14, 2024Updated 2 years ago
- Minimalistic RV32I RISC-V Processor in System Verilog☆32Sep 19, 2023Updated 2 years ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆28Sep 8, 2024Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆30Jun 22, 2024Updated 2 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆21Sep 2, 2023Updated 2 years ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆33Jul 21, 2025Updated last year
- ☆14Sep 29, 2024Updated last year
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Apr 11, 2023Updated 3 years ago
- A mixed-signal system on chip for nanopore-based DNA sequencing☆35Nov 30, 2022Updated 3 years ago
- Little cpu in verilog.☆11May 18, 2026Updated 2 months ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆17Apr 12, 2020Updated 6 years ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆172Nov 2, 2020Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Implementation of RV32I in Logisim-evolution.☆26Sep 19, 2023Updated 2 years ago
- To design test bench of the APB protocol☆21Dec 30, 2020Updated 5 years ago
- I2C master/slave Core☆15Jul 17, 2014Updated 12 years ago
- Arduino library for radio-controlled models using the CRSF protocol☆25Mar 12, 2025Updated last year
- This repository contains tutorial code and supplementary note for point cloud processing.☆12Jun 21, 2026Updated last month
- RV32I Implementation on TangNano9K☆12Dec 24, 2022Updated 3 years ago
- A Verilog RTL model of a simple 8-bit RISC processor☆20Jan 15, 2019Updated 7 years ago
- Scripts for aligning cryo-electron microscopy direct electron detector movies on whole movies or individual particle trajectories☆12Mar 28, 2017Updated 9 years ago
- ☆24Oct 28, 2025Updated 8 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- RISCV core RV32I/E.4 threads in a ring architecture☆34Jun 12, 2023Updated 3 years ago
- TFHE is a popular algorithm for homomorphic encryption. Staring with a C/C++ specification of TFHE to be provided, This project rewrite t…☆21May 27, 2024Updated 2 years ago
- Post-quantum cryptography (PQC) - Falcon☆19Apr 15, 2025Updated last year
- ☆12Mar 17, 2022Updated 4 years ago
- ☆31Feb 22, 2024Updated 2 years ago
- A bipedal humanoid control system using a Physics-Informed Neural Network (PINN) and Reinforcement Learning (RL) for stability and manipu…☆13Mar 25, 2026Updated 3 months ago
- I2C slave Verilog Design and TestBench☆27May 9, 2019Updated 7 years ago
- Repository containing matlab scripts and data used for system identification on a Parrot Bebop 2 drone.☆12Mar 27, 2020Updated 6 years ago
- SLOSH-ML is a Matlab graphical user interface designed to analyze rocket propellant sloshing in space launch vehicles☆19Mar 19, 2026Updated 4 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.☆15Aug 7, 2022Updated 3 years ago
- 🚀 Real-Time High-Level Synthesis (HLS) Projects for UltraScale+ FPGAs. Accelerated design pipelines, dataflow architectures, and low-lat…☆15Aug 25, 2025Updated 10 months ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆39Jun 2, 2021Updated 5 years ago
- Simple 3-stage pipeline RISC-V processor☆149Feb 24, 2026Updated 4 months ago
- A Linux-supported RISC-V SoC for FPGAs, described in Verilog HDL☆22May 14, 2026Updated 2 months ago
- Hardware Accelerators on FPGA for Computer Vision Applications☆15Dec 16, 2025Updated 7 months ago
- Nonlinear System Identification (aka Learning Dynamical Systems) with guaranteed stability/contraction☆14Dec 20, 2019Updated 6 years ago