Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
☆23Jul 7, 2024Updated 2 years ago
Alternatives and similar repositories for SPI_Serial_Peripheral_Interface_Verilog_Modules
Users that are interested in SPI_Serial_Peripheral_Interface_Verilog_Modules are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆21Dec 15, 2019Updated 6 years ago
- Hardware Viterbi Decoder in verilog☆31May 28, 2019Updated 7 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆15Aug 26, 2024Updated 2 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆41May 10, 2019Updated 7 years ago
- An 8 input interrupt controller written in Verilog.☆31Mar 22, 2012Updated 14 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆16Jun 28, 2021Updated 5 years ago
- An open-source Verilog implementation of Serial Peripheral Interface protocol with simulation support for efficient data exchange.☆16Dec 26, 2023Updated 2 years ago
- ☆16Jul 27, 2025Updated last year
- This is a SPI Master Module Written in Verilog☆14Aug 9, 2018Updated 8 years ago
- A wishbone controlled PWM (audio) controller☆19Jan 16, 2024Updated 2 years ago
- Solutions to HDLBits Verilog Problem Set☆55Jul 27, 2025Updated last year
- Interface Protocol in Verilog☆52Aug 2, 2019Updated 7 years ago
- ☆58Jun 19, 2021Updated 5 years ago
- Verilog Code for I2C Protocol☆20Nov 12, 2020Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- 基于w5500官方库ioLibrary_Driver,在STM32F103RC上实现了mqtt的功能☆12Jul 11, 2018Updated 8 years ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 8 years ago
- SystemVerilog Tutorial☆243Sep 27, 2026Updated 2 weeks ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- Verification IP project for I3C protocol☆29May 28, 2026Updated 4 months ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 3 years ago
- SPI interface connect to APB BUS with Verilog HDL☆43Jun 27, 2021Updated 5 years ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆17Aug 26, 2021Updated 5 years ago
- FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope☆14Sep 5, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- 16 bit CPU created in Vivado with Verilog☆23Jun 30, 2022Updated 4 years ago
- An automatic speaker recognition system built from digital signal processing tools, Vector Quantization and LBG algorithm☆11May 24, 2021Updated 5 years ago
- Simple implementation of I2C interface written on Verilog and SystemC☆49Aug 26, 2017Updated 9 years ago
- This Repository contains the Implementation of the AMBA APB4 Protocol with Verilog, featuring an APB master, APB slave with cache memory,…☆18Sep 5, 2024Updated 2 years ago
- APB Timer Unit☆14Oct 30, 2025Updated 11 months ago
- A PyTorch-based numerical simulator for decoders in quantum error correction.☆15Updated this week
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆36Mar 21, 2020Updated 6 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆20Jan 30, 2020Updated 6 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- Light modbus RTU Slave without SPL and HAL. This lib doesn't need timers, only UART and 2 channels of DMA.☆11Jun 25, 2019Updated 7 years ago
- ☆11Mar 12, 2024Updated 2 years ago
- Synchronous FIFO Testbench☆12Apr 17, 2022Updated 4 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 5 years ago
- stm32 HAL库使用内部RAM模拟U盘升级☆14Dec 4, 2020Updated 5 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆21Sep 14, 2023Updated 3 years ago