Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
☆23Jul 7, 2024Updated 2 years ago
Alternatives and similar repositories for SPI_Serial_Peripheral_Interface_Verilog_Modules
Users that are interested in SPI_Serial_Peripheral_Interface_Verilog_Modules are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆21Dec 15, 2019Updated 6 years ago
- Portal for 2024 SIT batch being mentored at the Advnaced VLSI Lab.☆11Apr 9, 2023Updated 3 years ago
- Hardware Viterbi Decoder in verilog☆32May 28, 2019Updated 7 years ago
- An 8 input interrupt controller written in Verilog.☆30Mar 22, 2012Updated 14 years ago
- An open-source Verilog implementation of Serial Peripheral Interface protocol with simulation support for efficient data exchange.☆16Dec 26, 2023Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆14Jul 27, 2025Updated 11 months ago
- This is a SPI Master Module Written in Verilog☆14Aug 9, 2018Updated 7 years ago
- A wishbone controlled PWM (audio) controller☆19Jan 16, 2024Updated 2 years ago
- Interface Protocol in Verilog☆52Aug 2, 2019Updated 6 years ago
- ☆56Jun 19, 2021Updated 5 years ago
- Verilog Code for I2C Protocol☆19Nov 12, 2020Updated 5 years ago
- Starting my 100 days verilog RTL, and basic system verilog coding challenge from , 21 may 2024☆25Mar 20, 2025Updated last year
- 基于w5500官方库ioLibrary_Driver,在STM32F103RC上实现了mqtt的功能☆12Jul 11, 2018Updated 8 years ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 8 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Verification IP project for I3C protocol☆28May 28, 2026Updated last month
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 2 years ago
- SPI interface connect to APB BUS with Verilog HDL☆43Jun 27, 2021Updated 5 years ago
- FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope☆14Sep 5, 2025Updated 10 months ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Sobel is first order or gradient based edge operator for images and it is implemented using verilog.☆14Dec 16, 2020Updated 5 years ago
- An automatic speaker recognition system built from digital signal processing tools, Vector Quantization and LBG algorithm☆10May 24, 2021Updated 5 years ago
- This Repository contains the Implementation of the AMBA APB4 Protocol with Verilog, featuring an APB master, APB slave with cache memory,…☆17Sep 5, 2024Updated last year
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆35Mar 21, 2020Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆20Jan 30, 2020Updated 6 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- Light modbus RTU Slave without SPL and HAL. This lib doesn't need timers, only UART and 2 channels of DMA.☆10Jun 25, 2019Updated 7 years ago
- ☆11Mar 12, 2024Updated 2 years ago
- Synchronous FIFO Testbench☆12Apr 17, 2022Updated 4 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 4 years ago
- stm32 HAL库使用内部RAM模拟U盘升级☆13Dec 4, 2020Updated 5 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆21Sep 14, 2023Updated 2 years ago
- Little RISC-V 3-stage Pipeline CPU☆16Jun 14, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Bot…☆17Aug 21, 2018Updated 7 years ago
- ☆15Jul 5, 2019Updated 7 years ago
- Polar Codes Implementation on Vhdl☆13Jun 4, 2016Updated 10 years ago
- I2C slave Verilog Design and TestBench☆27May 9, 2019Updated 7 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆208Jan 29, 2024Updated 2 years ago
- SystemVerilog examples and projects☆21Jun 10, 2025Updated last year
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆19Oct 6, 2024Updated last year