daringpatil3134 / SPI_Serial_Peripheral_Interface_Verilog_Modules
Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
☆11Updated 9 months ago
Alternatives and similar repositories for SPI_Serial_Peripheral_Interface_Verilog_Modules:
Users that are interested in SPI_Serial_Peripheral_Interface_Verilog_Modules are comparing it to the libraries listed below
- ☆17Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- Architectural design of data router in verilog☆29Updated 5 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated last year
- ☆43Updated 3 years ago
- System Verilog using Functional Verification☆10Updated last year
- ☆16Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆10Updated 8 months ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆27Updated 6 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆44Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- ☆12Updated 3 weeks ago
- Synchronous FIFO Testbench☆10Updated 3 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated last year
- SystemVerilog examples and projects☆17Updated 6 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- A Spiking Neuron Network Project in Verilog Implementation☆21Updated 7 years ago
- ☆16Updated last year
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆25Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆57Updated last year
- ☆16Updated 2 weeks ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆75Updated last year
- ☆16Updated last year
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆15Updated last year
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆88Updated last year
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆14Updated 2 years ago
- ☆10Updated 2 years ago