dineshannayya / riscduino_dcore
☆12Updated 7 months ago
Alternatives and similar repositories for riscduino_dcore:
Users that are interested in riscduino_dcore are comparing it to the libraries listed below
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- ☆40Updated 2 years ago
- ☆13Updated last year
- ☆12Updated this week
- ☆17Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆37Updated 3 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆40Updated 11 months ago
- Python Tool for UVM Testbench Generation☆50Updated 9 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆37Updated 3 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆43Updated 3 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Complete tutorial code.☆16Updated 9 months ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆64Updated 4 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆32Updated 2 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆37Updated 4 years ago
- This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…☆22Updated 3 years ago
- To design test bench of the APB protocol☆16Updated 4 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆14Updated 9 months ago
- ☆18Updated 4 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆54Updated 10 months ago
- Repository gathering basic modules for CDC purpose☆51Updated 5 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆10Updated this week
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- Xilinx AXI VIP example of use☆33Updated 3 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆54Updated 2 years ago