SkillSurf / systemverilog
SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow
☆33Updated 7 months ago
Alternatives and similar repositories for systemverilog:
Users that are interested in systemverilog are comparing it to the libraries listed below
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆35Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆64Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆64Updated 4 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆51Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆33Updated 10 months ago
- Implementing Different Adder Structures in Verilog☆60Updated 5 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆42Updated 4 years ago
- UVM and System Verilog Manuals☆38Updated 5 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆57Updated last month
- An 8 input interrupt controller written in Verilog.☆25Updated 12 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆44Updated last week
- This repository contains some introductory level review about learning about FPGA Design including some tutorials, links to websites and …☆31Updated this week
- ☆40Updated 2 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆34Updated 6 months ago
- Curriculum for a university course to teach chip design using open source EDA tools☆57Updated last year
- ☆16Updated last year
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆28Updated 2 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆53Updated 9 months ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 2 years ago
- Architectural design of data router in verilog☆28Updated 5 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆23Updated 2 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆86Updated 4 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆13Updated last year
- ☆27Updated 9 months ago
- ☆11Updated last week
- Introductory course into static timing analysis (STA).☆78Updated 2 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆31Updated 2 years ago
- ☆11Updated 6 months ago