SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow
☆52Feb 27, 2026Updated 3 weeks ago
Alternatives and similar repositories for systemverilog
Users that are interested in systemverilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆26Sep 8, 2024Updated last year
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 7 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Jan 6, 2023Updated 3 years ago
- SystemVerilog extension for Visual Studio Code☆14Dec 18, 2018Updated 7 years ago
- things about Verilog hardware description language☆17Sep 18, 2018Updated 7 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆26Feb 11, 2024Updated 2 years ago
- Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board☆18Apr 13, 2022Updated 3 years ago
- Some useful documents of Synopsys☆95Nov 5, 2021Updated 4 years ago
- Computer Vision and Image Processing algorithms implemented using OpenCV, NumPy and MatPlotLib, for UOM's EN2550 Fundamentals of Image P…☆28Nov 11, 2021Updated 4 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆14Jul 31, 2024Updated last year
- SystemVerilog Design Patterns☆26Mar 11, 2015Updated 11 years ago
- MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计☆22May 24, 2023Updated 2 years ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆33Feb 6, 2020Updated 6 years ago
- Compressed Sensing signal decoding with DNN oracle on STM32☆16Apr 5, 2021Updated 4 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Feb 17, 2026Updated last month
- Fault Injection Automatic Test Equipment☆16Nov 22, 2021Updated 4 years ago
- Implementation of a RISC-V CPU in Verilog.☆17Mar 2, 2025Updated last year
- 3-wide superscalar, out-of-order RISC-V processor (RV32IM subset) in System Verilog, demonstrating key Instruction-Level Parallelism☆26Aug 15, 2025Updated 7 months ago
- We made ISAC radar using Zedboard and AD9361, by receiving the transmitted chirp signals, calculating the autocorrelation and FFT to get …☆21Jan 11, 2025Updated last year
- Catalyst N1 — Open source neuromorphic processor (Loihi 1 parity). 128 cores, 131K neurons, 14-opcode learning ISA, FPGA-validated on AWS…☆19Mar 15, 2026Updated last week
- ARM Guide☆51Jan 4, 2024Updated 2 years ago
- This repository contains all the information included in the beginner SoC/physical design using open-source EDA tools organized by VLSI S…☆13Mar 7, 2021Updated 5 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆13Sep 28, 2022Updated 3 years ago
- An FPGA design for simulating biological neurons☆17Jul 5, 2024Updated last year
- 👾 Complete Quartus Project for FPGA-based-3D-renderer☆17Jul 13, 2021Updated 4 years ago
- [ICLR 2026] Learning to Parallel: Accelerating Diffusion Large Language Models via Learnable Parallel Decoding☆31Jan 27, 2026Updated last month
- usb-device implementation for Synopsys USB OTG IP cores☆51Oct 10, 2025Updated 5 months ago
- Black Duck Detect plugin for Jenkins☆12Nov 25, 2025Updated 3 months ago
- 9-bit SAR in skywater 130 nm☆17Jan 15, 2025Updated last year
- The development tree for OpenOCD for the Synopsys DesignWare ARC processor family☆15Aug 18, 2023Updated 2 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11May 29, 2021Updated 4 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆11Oct 3, 2017Updated 8 years ago
- Book repository "Analysis and Design of Elementary MOS Amplifier Stages"☆377Dec 22, 2025Updated 3 months ago
- Python script to transform a VCD file to wavedrom format☆84Aug 18, 2022Updated 3 years ago
- A simplified cache simulator for instructional purposes☆15Dec 30, 2020Updated 5 years ago
- Support code for DVCon 2021 paper submission☆12Mar 1, 2021Updated 5 years ago
- A dedicated graphical processor for ray tracing☆22Jun 7, 2021Updated 4 years ago
- USB Flashing Format (UF2) for your build.zig☆16Jul 23, 2024Updated last year