SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow
☆58Feb 27, 2026Updated 7 months ago
Alternatives and similar repositories for systemverilog
Users that are interested in systemverilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆28Sep 8, 2024Updated 2 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 8 years ago
- SystemVerilog extension for Visual Studio Code☆14Dec 18, 2018Updated 7 years ago
- things about Verilog hardware description language☆18Sep 18, 2018Updated 8 years ago
- 24bit CPU with integrated GPU made in Logisim☆15Mar 3, 2026Updated 7 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆33Feb 11, 2024Updated 2 years ago
- All the project files related to the development of an Arduino based autonomous mobile robot for UOM's EN2532 - Robot Design and Competit…☆11May 11, 2022Updated 4 years ago
- EN1060 lectures☆11Jan 25, 2026Updated 8 months ago
- Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board☆18Apr 13, 2022Updated 4 years ago
- Contains the ROS driver and firmware for the WGE100 camera used on the PR2 robot.☆16Mar 5, 2023Updated 3 years ago
- AWGN signal generator IP for FPGA implemented by Verilog HDL with Fmax up to 320MHz on Xilinx Virtex Ultra-Scale FPGA.☆16Sep 20, 2020Updated 6 years ago
- This is a tutorial on standard digital design flow☆86May 24, 2021Updated 5 years ago
- 100G Udp Link For axi Stream☆17Jun 27, 2023Updated 3 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆21Sep 14, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆19Jan 25, 2022Updated 4 years ago
- Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)☆47Jun 7, 2017Updated 9 years ago
- Engineering Program on RTL Design for FPGA Accelerator☆36Aug 1, 2020Updated 6 years ago
- This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codeba…☆31May 4, 2024Updated 2 years ago
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jul 1, 2026Updated 3 months ago
- Tapeouts done using OpenFASOC☆22Nov 3, 2025Updated 11 months ago
- SystemVerilog Design Patterns☆26Mar 11, 2015Updated 11 years ago
- Verilog RTL Design☆53Sep 4, 2021Updated 5 years ago
- This project presents the implementation of Quantum Key Distribution (QKD) Protocol:BB84 on FPGA. Quantum Communication Methodology has b…☆15Dec 29, 2022Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.☆33Nov 18, 2025Updated 10 months ago
- SystemVerilog Logger☆19Apr 6, 2026Updated 6 months ago
- SGMII☆14Jul 17, 2014Updated 12 years ago
- This is a code repo for previous projects in Digital Design & Verification☆20Jan 6, 2015Updated 11 years ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆34Feb 6, 2020Updated 6 years ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆53Mar 3, 2024Updated 2 years ago
- MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计☆21May 24, 2023Updated 3 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Mar 6, 2018Updated 8 years ago
- Implementation of a RISC-V CPU in Verilog.☆19Jun 27, 2026Updated 3 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Feb 17, 2026Updated 7 months ago
- Verilog-A model library for photonic devices and components used in electronics-photonics co-simulation☆25Feb 10, 2026Updated 8 months ago
- wafer.space GF180MCU Run 1☆42Oct 6, 2026Updated last week
- mysoltrk - a solar tracker, reinvented☆14Aug 22, 2023Updated 3 years ago
- Some useful documents of Synopsys☆119Nov 5, 2021Updated 4 years ago
- Thesis: Custom Filter Designs on the Red Pitaya☆13Jan 8, 2018Updated 8 years ago
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆14Sep 17, 2019Updated 7 years ago